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arm64: gicv3, add power up sequence for gc600/gc700 

Summary:
   GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
   Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
This commit is contained in:
qinwei1 2023-04-10 08:52:25 +08:00 committed by Alan Carvalho de Assis
parent 7990f90915
commit 28a354f276
2 changed files with 7 additions and 0 deletions
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1
arch/arm64/src/common/arm64_gic.h
View File

@ -195,6 +195,7 @@
#define GICR_TYPER 0x0008
#define GICR_STATUSR 0x0010
#define GICR_WAKER 0x0014
#define GICR_PWRR 0x0024
#define GICR_SETLPIR 0x0040
#define GICR_CLRLPIR 0x0048
#define GICR_PROPBASER 0x0070

6
arch/arm64/src/common/arm64_gicv3.c
View File

@ -299,6 +299,12 @@ static void gicv3_rdist_enable(unsigned long rdist)
return;
}
/* Power up sequence of the Redistributors for GIC600/GIC700
* please check GICR_PWRR define at trm of GIC600/GIC700
*/
putreg32(0x2, rdist + GICR_PWRR);
sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))