From 2443a4f55354f59f8b2b28def610323fb51b6430 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 18 Sep 2012 18:32:31 +0000 Subject: [PATCH] Cosmetic updates to the ENC28J60 driver git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5161 42af7a65-404d-4744-a932-0658087f49c3 --- README.txt | 2 +- drivers/net/enc28j60.c | 57 +++++++++++++++++++++++++++++++++++------- drivers/net/enc28j60.h | 5 ++-- 3 files changed, 51 insertions(+), 13 deletions(-) diff --git a/README.txt b/README.txt index d7587002a6..5c330aa683 100644 --- a/README.txt +++ b/README.txt @@ -466,7 +466,7 @@ Build Targets and Options This is the build "verbosity flag." If you specify V=1 on the make command line, you will see the exact commands used in the build. This can be very useful when adding new boards or tracking down compile time errors and - warnings. + warnings (Contributed by Richard Cochran). CYGWIN BUILD PROBLEMS ^^^^^^^^^^^^^^^^^^^^^ diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 3800cd019d..d5583d4279 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -925,7 +925,7 @@ static inline void enc_wrbuffer(FAR struct enc_driver_s *priv, */ enc_deselect(priv); - enc_bmdump(ENC_WBM, buffer, buflen); + enc_bmdump(ENC_WBM, buffer, buflen+1); } /**************************************************************************** @@ -949,20 +949,38 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr) { uint16_t data = 0; - /* Set the PHY address (and start the PHY read operation) */ + /* "To read from a PHY register: + * + * 1. Write the address of the PHY register to read from into the MIREGADR + * register. + */ enc_wrbreg(priv, ENC_MIREGADR, phyaddr); + + /* 2. Set the MICMD.MIIRD bit. The read operation begins and the + * MISTAT.BUSY bit is set. + */ + enc_wrbreg(priv, ENC_MICMD, MICMD_MIIRD); - /* Wait until the PHY read completes */ + /* 3. Wait 10.24 µs. Poll the MISTAT.BUSY bit to be certain that the + * operation is complete. While busy, the host controller should not + * start any MIISCAN operations or write to the MIWRH register. + * + * When the MAC has obtained the register contents, the BUSY bit will + * clear itself. + */ + up_udelay(12); if (enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00) == OK); { - /* Terminate reading */ + /* 4. Clear the MICMD.MIIRD bit. */ enc_wrbreg(priv, ENC_MICMD, 0x00); - /* Get the PHY data */ + /* 5. Read the desired data from the MIRDL and MIRDH registers. The + * order that these bytes are accessed is unimportant." + */ data = (uint16_t)enc_rdbreg(priv, ENC_MIRDL); data |= (uint16_t)enc_rdbreg(priv, ENC_MIRDH) << 8; @@ -992,17 +1010,35 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr) static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr, uint16_t phydata) { - /* Set the PHY register address */ + /* "To write to a PHY register: + * + * 1. Write the address of the PHY register to write to into the + * MIREGADR register. + */ enc_wrbreg(priv, ENC_MIREGADR, phyaddr); - /* Write the PHY data */ + /* 2. Write the lower 8 bits of data to write into the MIWRL register. */ enc_wrbreg(priv, ENC_MIWRL, phydata); + + /* 3. Write the upper 8 bits of data to write into the MIWRH register. + * Writing to this register automatically begins the MIIM transaction, + * so it must be written to after MIWRL. The MISTAT.BUSY bit becomes + * set. + */ + enc_wrbreg(priv, ENC_MIWRH, phydata >> 8); - /* Wait until the PHY write completes */ + /* The PHY register will be written after the MIIM operation completes, + * which takes 10.24 µs. When the write operation has completed, the BUSY + * bit will clear itself. + * + * The host controller should not start any MIISCAN or MIIRD operations + * while busy." + */ + up_udelay(12); enc_waitbreg(priv, ENC_MISTAT, MISTAT_BUSY, 0x00); } @@ -1063,7 +1099,10 @@ static int enc_transmit(FAR struct enc_driver_s *priv) enc_wrbreg(priv, ENC_EWRPTL, PKTMEM_TX_START & 0xff); enc_wrbreg(priv, ENC_EWRPTH, PKTMEM_TX_START >> 8); - /* Set the TX End pointer based on the size of the packet to send */ + /* Set the TX End pointer based on the size of the packet to send. Note + * that the offset accounts for the control byte at the beginning the + * buffer plus the size of the packet data. + */ txend = PKTMEM_TX_START + priv->dev.d_len; enc_wrbreg(priv, ENC_ETXNDL, txend & 0xff); diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h index 446ca8e3e8..6f7f8f4652 100644 --- a/drivers/net/enc28j60.h +++ b/drivers/net/enc28j60.h @@ -360,8 +360,8 @@ /* PHY Control Register 1 Register Bit Definitions */ -#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */ -#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power Save */ +#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Duplex Mode */ +#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */ #define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */ #define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */ @@ -399,7 +399,6 @@ #define PHIR_PLNKIF (1 << 4) /* Bit 4: PHY Link Change Interrupt */ /* PHLCON Regiser Bit Definitions */ - /* Bit 0: Reserved */ #define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */ #define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */