arch/pic32mz: Serial TIOCxBRK BSD-compatible BREAK support
In the lower half UART driver for PIC32MZ architecture, adding the TIOCxBRK ioctl calls, which allow an application to transmit a UART line BREAK signal. This architecture does not support BSD-style BREAK in hardware so our implementation follows the precedent set in STM32, GD32, and Kinetis architectures: By default, if only PIC32MZ_UART_BREAKS is configured, we produce the hardware-native BREAK, which lasts for 12 bit lengths; if, in addition, PIC32MZ_SERIALBRK_BSDCOMPAT is configured, we generate a BSD-style BREAK by putting the TX pin in GPIO mode and driving it low "manually" until told to stop. * arch/mips/src/pic32mz/Kconfig (config PIC32MZ_UART_BREAKS): New. Appears as CONFIG_PIC32MZ_UART_BREAKS in code. (config PIC32MZ_SERIALBRK_BSDCOMPAT): New. Appears as CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT in code. * arch/mips/src/pic32mz/hardware/pic32mz_pps.h (__PPS_OUTPUT_REGADDR_TO_GPIO, PPS_OUTPUT_REGADDR_TO_GPIO): New macros to automatically determine the GPIO port and pin from the corresponding PPS (Peripheral Pin Select) define. Since there is a one-to-one correspondence between PPS output mappings and a single port and pin, these macros avoid writing redundant pin mappings. We use this when switching the TX pin from UART to GPIO to generate the BREAK and we could use it in other peripheral drivers in the future to override hardware behavior. * arch/mips/src/pic32mz/pic32mz_serial.c (struct up_dev_s): Add new field 'brk' to indicate line break in progress when built with PIC32MZ_UART_BREAKS. If generating BSD- compatible BREAKs, also add tx_gpio, tx_pps_reg, and tx_pps_val, to let us toggle the pin between UART and GPIO modes. (up_ioctl): Add cases for TIOCSBRK and TIOCCBRK to turn BREAK on and off, with both hardware-native and BSD-compatible implementations. This is similar to the STM32F7 implementation. (up_txint): Block enabling TX interrupt if line break in progress. This is similar to the STM32F7 implementation.
This commit is contained in:
Nathan Hartman
Xiang Xiao
parent
461cd4c4c5
commit
1d5c8380b1
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@ -261,6 +261,27 @@ config PIC32MZ_UART6
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select UART6_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config PIC32MZ_UART_BREAKS
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bool "Add TIOxSBRK to support sending Breaks"
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depends on PIC32MZ_UART1 || PIC32MZ_UART2 || PIC32MZ_UART3 || PIC32MZ_UART4 || PIC32MZ_UART5 || PIC32MZ_UART6
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default n
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---help---
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Add TIOCxBRK routines to send a line break per the PIC32MZ manual.
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The break consists of a start bit, 12 zero bits, and a stop bit.
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This is not a BSD compatible break.
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config PIC32MZ_SERIALBRK_BSDCOMPAT
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bool "Use GPIO to send Break"
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depends on PIC32MZ_UART_BREAKS
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default n
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---help---
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Enable using GPIO on the TX pin to send a BSD compatible break:
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TIOCSBRK will start the break and TIOCCBRK will end the break. The
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current PIC32MZ UARTS have no way to leave the break on (TX=LOW)
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because software starts the break and then the hardware
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automatically clears the break. This makes it difficult to send a
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long break.
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config PIC32MZ_ADC
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bool "ADC1"
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default n
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@ -76,6 +76,74 @@
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#define __PPS_OUTPUT_REGVAL(a,b) ((uint32_t)(a))
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#define PPS_OUTPUT_REGVAL(a) __PPS_OUTPUT_REGVAL(a)
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/* The following macro converts from a peripheral output pin mapping to the
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* corresponding GPIO port and pin. This allows drivers to do things like
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* temporarily change a pin's configuration from peripheral to GPIO to
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* override some hardware behavior. Having this macro available to driver
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* code relieves the board's include/board.h from redundantly defining both
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* the PPS mapping and the GPIO port/pin information.
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*
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* NOTE: This is written in the same odd macro forms as above for the same
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* reason.
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*/
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#define __PPS_OUTPUT_REGADDR_TO_GPIO(a,b) ((uint32_t)( \
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((b) == PIC32MZ_RPA14R) ? (GPIO_PORTA | GPIO_PIN14) : \
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((b) == PIC32MZ_RPA15R) ? (GPIO_PORTA | GPIO_PIN15) : \
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((b) == PIC32MZ_RPB0R) ? (GPIO_PORTB | GPIO_PIN0) : \
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((b) == PIC32MZ_RPB10R) ? (GPIO_PORTB | GPIO_PIN10) : \
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((b) == PIC32MZ_RPB14R) ? (GPIO_PORTB | GPIO_PIN14) : \
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((b) == PIC32MZ_RPB15R) ? (GPIO_PORTB | GPIO_PIN15) : \
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((b) == PIC32MZ_RPB1R) ? (GPIO_PORTB | GPIO_PIN1) : \
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((b) == PIC32MZ_RPB2R) ? (GPIO_PORTB | GPIO_PIN2) : \
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((b) == PIC32MZ_RPB3R) ? (GPIO_PORTB | GPIO_PIN3) : \
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((b) == PIC32MZ_RPB5R) ? (GPIO_PORTB | GPIO_PIN5) : \
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((b) == PIC32MZ_RPB6R) ? (GPIO_PORTB | GPIO_PIN6) : \
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((b) == PIC32MZ_RPB7R) ? (GPIO_PORTB | GPIO_PIN7) : \
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((b) == PIC32MZ_RPB8R) ? (GPIO_PORTB | GPIO_PIN8) : \
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((b) == PIC32MZ_RPB9R) ? (GPIO_PORTB | GPIO_PIN9) : \
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((b) == PIC32MZ_RPC13R) ? (GPIO_PORTC | GPIO_PIN13) : \
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((b) == PIC32MZ_RPC14R) ? (GPIO_PORTC | GPIO_PIN14) : \
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((b) == PIC32MZ_RPC1R) ? (GPIO_PORTC | GPIO_PIN1) : \
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((b) == PIC32MZ_RPC2R) ? (GPIO_PORTC | GPIO_PIN2) : \
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((b) == PIC32MZ_RPC3R) ? (GPIO_PORTC | GPIO_PIN3) : \
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((b) == PIC32MZ_RPC4R) ? (GPIO_PORTC | GPIO_PIN4) : \
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((b) == PIC32MZ_RPD0R) ? (GPIO_PORTD | GPIO_PIN0) : \
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((b) == PIC32MZ_RPD10R) ? (GPIO_PORTD | GPIO_PIN10) : \
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((b) == PIC32MZ_RPD11R) ? (GPIO_PORTD | GPIO_PIN11) : \
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((b) == PIC32MZ_RPD12R) ? (GPIO_PORTD | GPIO_PIN12) : \
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((b) == PIC32MZ_RPD14R) ? (GPIO_PORTD | GPIO_PIN14) : \
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((b) == PIC32MZ_RPD15R) ? (GPIO_PORTD | GPIO_PIN15) : \
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((b) == PIC32MZ_RPD1R) ? (GPIO_PORTD | GPIO_PIN1) : \
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((b) == PIC32MZ_RPD2R) ? (GPIO_PORTD | GPIO_PIN2) : \
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((b) == PIC32MZ_RPD3R) ? (GPIO_PORTD | GPIO_PIN3) : \
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((b) == PIC32MZ_RPD4R) ? (GPIO_PORTD | GPIO_PIN4) : \
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((b) == PIC32MZ_RPD5R) ? (GPIO_PORTD | GPIO_PIN5) : \
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((b) == PIC32MZ_RPD6R) ? (GPIO_PORTD | GPIO_PIN6) : \
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((b) == PIC32MZ_RPD7R) ? (GPIO_PORTD | GPIO_PIN7) : \
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((b) == PIC32MZ_RPD9R) ? (GPIO_PORTD | GPIO_PIN9) : \
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((b) == PIC32MZ_RPE3R) ? (GPIO_PORTE | GPIO_PIN3) : \
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((b) == PIC32MZ_RPE5R) ? (GPIO_PORTE | GPIO_PIN5) : \
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((b) == PIC32MZ_RPE8R) ? (GPIO_PORTE | GPIO_PIN8) : \
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((b) == PIC32MZ_RPE9R) ? (GPIO_PORTE | GPIO_PIN9) : \
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((b) == PIC32MZ_RPF0R) ? (GPIO_PORTF | GPIO_PIN0) : \
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((b) == PIC32MZ_RPF12R) ? (GPIO_PORTF | GPIO_PIN12) : \
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((b) == PIC32MZ_RPF13R) ? (GPIO_PORTF | GPIO_PIN13) : \
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((b) == PIC32MZ_RPF1R) ? (GPIO_PORTF | GPIO_PIN1) : \
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((b) == PIC32MZ_RPF2R) ? (GPIO_PORTF | GPIO_PIN2) : \
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((b) == PIC32MZ_RPF3R) ? (GPIO_PORTF | GPIO_PIN3) : \
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((b) == PIC32MZ_RPF4R) ? (GPIO_PORTF | GPIO_PIN4) : \
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((b) == PIC32MZ_RPF5R) ? (GPIO_PORTF | GPIO_PIN5) : \
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((b) == PIC32MZ_RPF8R) ? (GPIO_PORTF | GPIO_PIN8) : \
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((b) == PIC32MZ_RPG0R) ? (GPIO_PORTG | GPIO_PIN0) : \
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((b) == PIC32MZ_RPG1R) ? (GPIO_PORTG | GPIO_PIN1) : \
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((b) == PIC32MZ_RPG6R) ? (GPIO_PORTG | GPIO_PIN6) : \
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((b) == PIC32MZ_RPG7R) ? (GPIO_PORTG | GPIO_PIN7) : \
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((b) == PIC32MZ_RPG8R) ? (GPIO_PORTG | GPIO_PIN8) : \
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((b) == PIC32MZ_RPG9R) ? (GPIO_PORTG | GPIO_PIN9) : \
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0 \
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))
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#define PPS_OUTPUT_REGADDR_TO_GPIO(a) __PPS_OUTPUT_REGADDR_TO_GPIO(a)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -49,6 +49,11 @@
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#include "hardware/pic32mz_uart.h"
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#include "pic32mz_lowconsole.h"
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#ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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# include "pic32mz_gpio.h"
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# include "hardware/pic32mz_pps.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -232,15 +237,24 @@
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struct up_dev_s
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{
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uintptr_t uartbase; /* Base address of UART registers */
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uint32_t baud; /* Configured baud */
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uint8_t irqe; /* Error IRQ associated with this UART (for enable) */
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uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */
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uint8_t irqtx; /* TX IRQ associated with this UART (for enable) */
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uint8_t im; /* Interrupt mask state */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5, 6, 7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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uintptr_t uartbase; /* Base address of UART registers */
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uint32_t baud; /* Configured baud */
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uint8_t irqe; /* Error IRQ associated with this UART (for enable) */
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uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */
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uint8_t irqtx; /* TX IRQ associated with this UART (for enable) */
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uint8_t im; /* Interrupt mask state */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (5, 6, 7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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bool brk; /* true: Line break in progress */
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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const uint32_t tx_gpio; /* GPIO config to put TX pin in GPIO mode */
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const uintptr_t tx_pps_reg; /* PPS register to toggle UART/GPIO modes */
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const uint8_t tx_pps_val; /* PPS value to restore pin to UART mode */
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# endif
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#endif
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};
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/****************************************************************************
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@ -334,6 +348,16 @@ static struct up_dev_s g_uart1priv =
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.parity = CONFIG_UART1_PARITY,
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.bits = CONFIG_UART1_BITS,
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.stopbits2 = CONFIG_UART1_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U1TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U1TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U1TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart1port =
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@ -366,6 +390,16 @@ static struct up_dev_s g_uart2priv =
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.parity = CONFIG_UART2_PARITY,
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.bits = CONFIG_UART2_BITS,
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.stopbits2 = CONFIG_UART2_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U2TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U2TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U2TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart2port =
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@ -398,6 +432,16 @@ static struct up_dev_s g_uart3priv =
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.parity = CONFIG_UART3_PARITY,
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.bits = CONFIG_UART3_BITS,
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.stopbits2 = CONFIG_UART3_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U3TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U3TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U3TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart3port =
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@ -430,6 +474,16 @@ static struct up_dev_s g_uart4priv =
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.parity = CONFIG_UART4_PARITY,
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.bits = CONFIG_UART4_BITS,
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.stopbits2 = CONFIG_UART4_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U4TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U4TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U4TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart4port =
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@ -462,6 +516,16 @@ static struct up_dev_s g_uart5priv =
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.parity = CONFIG_UART5_PARITY,
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.bits = CONFIG_UART5_BITS,
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.stopbits2 = CONFIG_UART5_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U5TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U5TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U5TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart5port =
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@ -494,6 +558,16 @@ static struct up_dev_s g_uart6priv =
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.parity = CONFIG_UART6_PARITY,
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.bits = CONFIG_UART6_BITS,
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.stopbits2 = CONFIG_UART6_2STOP,
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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.brk = false,
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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.tx_gpio = PPS_OUTPUT_REGADDR_TO_GPIO(BOARD_U6TX_PPS)
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| GPIO_OUTPUT | GPIO_VALUE_ZERO,
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.tx_pps_reg = PPS_OUTPUT_REGADDR(BOARD_U6TX_PPS),
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.tx_pps_val = PPS_OUTPUT_REGVAL(BOARD_U6TX_PPS),
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# endif
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#endif
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};
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static uart_dev_t g_uart6port =
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@ -811,11 +885,12 @@ static int up_interrupt(int irq, void *context, void *arg)
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static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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{
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#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS)
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#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
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|| defined(CONFIG_PIC32MZ_UART_BREAKS)
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struct inode *inode = filep->f_inode;
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struct uart_dev_s *dev = inode->i_private;
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#endif
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#if defined(CONFIG_SERIAL_TERMIOS)
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#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_PIC32MZ_UART_BREAKS)
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struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
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#endif
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int ret = OK;
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@ -945,6 +1020,101 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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break;
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#endif /* CONFIG_SERIAL_TERMIOS */
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#ifdef CONFIG_PIC32MZ_UART_BREAKS
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# ifdef CONFIG_PIC32MZ_SERIALBRK_BSDCOMPAT
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case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
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{
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irqstate_t flags;
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flags = enter_critical_section();
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/* Disable any further TX activity */
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priv->brk = true;
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up_txint(dev, false);
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/* Configure TX as a GPIO output pin driven low to send break */
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pic32mz_configgpio(priv->tx_gpio);
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putreg32(0, priv->tx_pps_reg);
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leave_critical_section(flags);
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}
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break;
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case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
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{
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irqstate_t flags;
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flags = enter_critical_section();
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/* Configure TX back to UART */
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putreg32(priv->tx_pps_val, priv->tx_pps_reg);
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/* Enable further tx activity */
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priv->brk = false;
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up_txint(dev, true);
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leave_critical_section(flags);
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}
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break;
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# else
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case TIOCSBRK: /* No BSD compatibility: Turn break on for 12 bit times */
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{
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uint32_t regval;
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irqstate_t flags;
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flags = enter_critical_section();
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/* Disable any further TX activity */
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priv->brk = true;
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up_txint(dev, false);
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/* Enable break transmission */
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regval = up_serialin(priv, PIC32MZ_UART_STA_OFFSET);
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regval |= UART_STA_UTXBRK;
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up_serialout(priv, PIC32MZ_UART_STA_OFFSET, regval);
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/* A dummy write to TXREG is needed to start sending the break. The
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* caller should ensure that there are no pending transmit data in
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* the UART FIFO before executing this IOCTL or the break will
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* consume a byte of that data instead of the dummy write.
|
||||
*/
|
||||
|
||||
up_send(dev, 0);
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
|
||||
case TIOCCBRK: /* No BSD compatibility: May turn off break too soon */
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Enable further tx activity. We do not clear the UTXBRK bit
|
||||
* because hardware does it automatically after transmitting the
|
||||
* break. In fact, the PIC32MZ manual, rev G, section 21.5.4, says:
|
||||
* "If the user application clears the UTXBRK bit prior to sequence
|
||||
* completion, unexpected module behavior can result." It should be
|
||||
* safe to re-enable transmit here because the hardware specifically
|
||||
* allows to queue up the next character to follow the break.
|
||||
*/
|
||||
|
||||
priv->brk = false;
|
||||
up_txint(dev, true);
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
# endif
|
||||
#endif
|
||||
|
||||
default:
|
||||
ret = -ENOTTY;
|
||||
break;
|
||||
|
|
@ -1075,6 +1245,16 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
|||
/* Enable the TX interrupt */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
# ifdef CONFIG_PIC32MZ_UART_BREAKS
|
||||
/* Do not enable TX interrupt if line break in progress */
|
||||
|
||||
if (priv->brk)
|
||||
{
|
||||
leave_critical_section(flags);
|
||||
return;
|
||||
}
|
||||
# endif
|
||||
|
||||
up_enable_irq(priv->irqtx);
|
||||
ENABLE_TX(im);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue