arch/armv7[a|r]: Support non SGI in up_trigger_irq
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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@ -523,7 +523,21 @@ int up_prioritize_irq(int irq, int priority)
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void up_trigger_irq(int irq, cpu_set_t cpuset)
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void up_trigger_irq(int irq, cpu_set_t cpuset)
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{
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{
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arm_cpu_sgi(irq, cpuset);
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if (irq >= 0 && irq <= GIC_IRQ_SGI15)
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{
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arm_cpu_sgi(irq, cpuset);
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}
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else if (irq >= 0 && irq < NR_IRQS)
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{
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uintptr_t regaddr;
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/* Write '1' to the corresponding bit in the distributor Interrupt
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* Set-Pending (ICDISPR)
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*/
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regaddr = GIC_ICDISPR(irq);
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putreg32(GIC_ICDISPR_INT(irq), regaddr);
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}
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}
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}
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/****************************************************************************
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/****************************************************************************
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@ -522,7 +522,21 @@ int up_prioritize_irq(int irq, int priority)
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void up_trigger_irq(int irq, cpu_set_t cpuset)
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void up_trigger_irq(int irq, cpu_set_t cpuset)
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{
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{
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arm_cpu_sgi(irq, cpuset);
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if (irq >= 0 && irq <= GIC_IRQ_SGI15)
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{
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arm_cpu_sgi(irq, cpuset);
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}
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else if (irq >= 0 && irq < NR_IRQS)
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{
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uintptr_t regaddr;
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/* Write '1' to the corresponding bit in the distributor Interrupt
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* Set-Pending (ICDISPR)
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*/
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regaddr = GIC_ICDISPR(irq);
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putreg32(GIC_ICDISPR_INT(irq), regaddr);
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}
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}
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}
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#endif /* CONFIG_ARMV7R_HAVE_GICv2 */
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#endif /* CONFIG_ARMV7R_HAVE_GICv2 */
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