arm/armv[7|8]-m: add syn barrier for MPU ops
Execute data and instruction sync barriers after writing MPU register, to ensure MPU setting take effects that the new changes are seen. testing in lm3s6965-ek:qemu-protected Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
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@ -29,6 +29,7 @@
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#include "mpu.h"
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#include "arm_internal.h"
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#include "barriers.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -201,6 +202,9 @@ static void mpu_reset_internal()
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}
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putreg32(0, MPU_CTRL);
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ARM_DSB();
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ARM_ISB();
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}
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#endif
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@ -356,6 +360,11 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
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}
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putreg32(regval, MPU_CTRL);
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/* Ensure MPU setting take effects */
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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@ -413,6 +422,11 @@ void mpu_configure_region(uintptr_t base, size_t size,
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((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
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flags;
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putreg32(regval, MPU_RASR);
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/* Ensure MPU setting take effects */
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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@ -29,6 +29,7 @@
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#include "mpu.h"
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#include "arm_internal.h"
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#include "barriers.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -95,6 +96,9 @@ static void mpu_reset_internal()
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}
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putreg32(0, MPU_CTRL);
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ARM_DSB();
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ARM_ISB();
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}
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#endif
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@ -139,6 +143,11 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
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}
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putreg32(regval, MPU_CTRL);
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/* Ensure MPU setting take effects */
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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@ -174,6 +183,11 @@ void mpu_configure_region(uintptr_t base, size_t size,
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putreg32(base | flags1, MPU_RBAR);
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putreg32(limit | flags2 | MPU_RLAR_ENABLE, MPU_RLAR);
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/* Ensure MPU setting take effects */
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ARM_DSB();
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ARM_ISB();
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}
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/****************************************************************************
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