libs/libc/machine/risc-v: add rv32 support
Change-Id: I96a02aacea4e1d034f986f2937fe496da1f486ba Signed-off-by: ligd <liguiding@fishsemi.com>
This commit is contained in:
ligd
Alan Carvalho de Assis
parent
36a0978952
commit
0fe2884713
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@ -21,3 +21,7 @@
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ifeq ($(CONFIG_ARCH_RV64GC),y)
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include $(TOPDIR)/libs/libc/machine/risc-v/rv64/Make.defs
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endif
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ifeq ($(CONFIG_ARCH_RV32IM),y)
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include $(TOPDIR)/libs/libc/machine/risc-v/rv32/Make.defs
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endif
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@ -0,0 +1,10 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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config RISCV_MEMCPY
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bool "Enable optimized memcpy() for RISC-V"
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select LIBC_ARCH_MEMCPY
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---help---
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Enable optimized RISC-V specific memcpy() library function
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@ -0,0 +1,29 @@
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############################################################################
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# libs/libc/machine/risc-v/rv32/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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ifeq ($(CONFIG_RISCV_MEMCPY),y)
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ASRCS += arch_memcpy.S
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DEPPATH += --dep-path machine/risc-v/rv32
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VPATH += :machine/risc-v/rv32
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endif
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@ -0,0 +1,130 @@
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/****************************************************************************
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* libs/libc/machine/risc-v/rv32/arch_memcpy.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/************************************************************************************
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* Public Symbols
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************************************************************************************/
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.globl memcpy
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.file "arch_memcpy.S"
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/************************************************************************************
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* Name: memcpy
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************************************************************************************/
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.text
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memcpy:
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move t6, a0 /* Preserve return value */
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/* Defer to byte-oriented copy for small sizes */
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sltiu a3, a2, 128
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bnez a3, 4f
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/* Use word-oriented copy only if low-order bits match */
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andi a3, t6, 3
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andi a4, a1, 3
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bne a3, a4, 4f
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beqz a3, 2f /* Skip if already aligned */
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/*
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* Round to nearest double word-aligned address
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* greater than or equal to start address
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*/
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andi a3, a1, ~3
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addi a3, a3, 4
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/* Handle initial misalignment */
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sub a4, a3, a1
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1:
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lb a5, 0(a1)
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addi a1, a1, 1
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sb a5, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 1b
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sub a2, a2, a4 /* Update count */
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2:
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andi a4, a2, ~63
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beqz a4, 4f
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add a3, a1, a4
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3:
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lw a4, 0(a1)
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lw a5, 4(a1)
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lw a6, 2*4(a1)
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lw a7, 3*4(a1)
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lw t0, 4*4(a1)
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lw t1, 5*4(a1)
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lw t2, 6*4(a1)
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lw t3, 7*4(a1)
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lw t4, 8*4(a1)
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lw t5, 9*4(a1)
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sw a4, 0(t6)
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sw a5, 4(t6)
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sw a6, 2*4(t6)
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sw a7, 3*4(t6)
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sw t0, 4*4(t6)
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sw t1, 5*4(t6)
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sw t2, 6*4(t6)
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sw t3, 7*4(t6)
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sw t4, 8*4(t6)
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sw t5, 9*4(t6)
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lw a4, 10*4(a1)
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lw a5, 11*4(a1)
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lw a6, 12*4(a1)
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lw a7, 13*4(a1)
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lw t0, 14*4(a1)
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lw t1, 15*4(a1)
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addi a1, a1, 16*4
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sw a4, 10*4(t6)
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sw a5, 11*4(t6)
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sw a6, 12*4(t6)
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sw a7, 13*4(t6)
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sw t0, 14*4(t6)
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sw t1, 15*4(t6)
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addi t6, t6, 16*4
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bltu a1, a3, 3b
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andi a2, a2, 63 /* Update count */
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4:
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/* Handle trailing misalignment */
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beqz a2, 6f
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add a3, a1, a2
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/* Use word-oriented copy if co-aligned to word boundary */
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or a5, a1, t6
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or a5, a5, a3
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andi a5, a5, 3
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bnez a5, 5f
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7:
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lw a4, 0(a1)
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addi a1, a1, 4
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sw a4, 0(t6)
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addi t6, t6, 4
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bltu a1, a3, 7b
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ret
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5:
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lb a4, 0(a1)
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addi a1, a1, 1
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sb a4, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 5b
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6:
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ret
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