From 0eb1afcdef4a9f339ad01e6803c33d212e1e2307 Mon Sep 17 00:00:00 2001 From: petekol Date: Wed, 30 Sep 2015 17:13:32 +0200 Subject: [PATCH] usb reset right --- arch/arm/include/lpc43xx/chip.h | 2 +- arch/arm/src/lpc43xx/lpc43_cgu.c | 2 +- arch/arm/src/lpc43xx/lpc43_usb0dev.c | 4 +--- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h index 7c02b7b16c..80faf49bc3 100644 --- a/arch/arm/include/lpc43xx/chip.h +++ b/arch/arm/include/lpc43xx/chip.h @@ -46,7 +46,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 � 4 June 2012 */ +/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 4 June 2012 */ /* Get customizations for each supported chip. * * SRAM Resources diff --git a/arch/arm/src/lpc43xx/lpc43_cgu.c b/arch/arm/src/lpc43xx/lpc43_cgu.c index a50f5e93fa..6b13ee4fd7 100644 --- a/arch/arm/src/lpc43xx/lpc43_cgu.c +++ b/arch/arm/src/lpc43xx/lpc43_cgu.c @@ -461,7 +461,7 @@ void lpc43_pll0usbenable(void) * operation and will make the lock signal high once it has regained * lock on the input clock * - * Wait for PLL1 to report that it is locked. + * Wait for PLL0 to report that it is locked. */ while ((getreg32(LPC43_PLL0USB_STAT) & PLL0USB_STAT_LOCK) == 0); diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 0f09d91c28..2498862e0b 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -2667,9 +2667,7 @@ void up_usbinitialize(void) /* Reset USB block */ - regval = lpc43_getreg(LPC43_RGU_CTRL0); - regval |= RGU_CTRL0_USB0_RST; - lpc43_putreg(regval, LPC43_RGU_CTRL0); + lpc43_putreg(RGU_CTRL0_USB0_RST, LPC43_RGU_CTRL0); /* Reset the controller */