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assert:read content of undefinedinsn address 

read content of undefinedinsn address, and compare it with what it is in elf  to check if there is a ram bit flip

Signed-off-by: liaoao <liaoao@xiaomi.com>
This commit is contained in:
liaoao 2023-11-09 12:18:51 +08:00 committed by Xiang Xiao
parent eb2f661170
commit 0e2bf8ce2c
5 changed files with 42 additions and 4 deletions
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11
arch/arm/src/arm/arm_undefinedinsn.c
View File

@ -42,7 +42,16 @@
void arm_undefinedinsn(uint32_t *regs) void arm_undefinedinsn(uint32_t *regs)
{ {
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
regs[REG_PC], *(uint32_t *)regs[REG_PC]);
}
else
{
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
}
up_set_current_regs(regs); up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);

11
arch/arm/src/armv7-a/arm_undefinedinsn.c
View File

@ -42,7 +42,16 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
regs[REG_PC], *(uint32_t *)regs[REG_PC]);
}
else
{
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
}
up_set_current_regs(regs); up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);

11
arch/arm/src/armv7-r/arm_undefinedinsn.c
View File

@ -42,7 +42,16 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
regs[REG_PC], *(uint32_t *)regs[REG_PC]);
}
else
{
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
}
up_set_current_regs(regs); up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);

11
arch/arm/src/armv8-r/arm_undefinedinsn.c
View File

@ -42,7 +42,16 @@
uint32_t *arm_undefinedinsn(uint32_t *regs) uint32_t *arm_undefinedinsn(uint32_t *regs)
{ {
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]); if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
{
_alert("Undefined instruction at 0x%" PRIx32 ": 0x%" PRIx32 "\n",
regs[REG_PC], *(uint32_t *)regs[REG_PC]);
}
else
{
_alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
}
up_set_current_regs(regs); up_set_current_regs(regs);
PANIC_WITH_REGS("panic", regs); PANIC_WITH_REGS("panic", regs);

2
boards/arm/lpc31xx/ea3131/scripts/pg-ld.script
View File

@ -99,6 +99,7 @@ SECTIONS
.paged : { .paged : {
_spaged = ABSOLUTE(.); _spaged = ABSOLUTE(.);
_stext = _spaged;
*(.text .text.*) *(.text .text.*)
*(.fixup) *(.fixup)
*(.gnu.warning) *(.gnu.warning)
@ -110,6 +111,7 @@ SECTIONS
*(.gcc_except_table) *(.gcc_except_table)
*(.gnu.linkonce.r.*) *(.gnu.linkonce.r.*)
_epaged = ABSOLUTE(.); _epaged = ABSOLUTE(.);
_etext = _epaged;
} > paged } > paged
.data : { .data : {