diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
index 9d2a645e0c..25f8c33e9b 100644
--- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
@@ -883,7 +883,7 @@ static void stm32_stdclockconfig(void)
         {
         }
 #endif
-#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
+#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
 
       /* Configure PLLI2S */
 
@@ -898,6 +898,19 @@ static void stm32_stdclockconfig(void)
                  | STM32_RCC_PLLSAICFGR_PLLSAIR);
       putreg32(regval, STM32_RCC_PLLI2SCFGR);
 
+      /* Enable PLLI2S */
+
+      regval = getreg32(STM32_RCC_CR);
+      regval |= RCC_CR_PLLI2SON;
+      putreg32(regval, STM32_RCC_CR);
+
+      /* Wait until the PLLI2S is ready */
+
+      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
+        {
+        }
+#endif
+
       regval  = getreg32(STM32_RCC_DCKCFGR2);
       regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
                   | RCC_DCKCFGR2_USART2SEL_MASK
@@ -937,19 +950,6 @@ static void stm32_stdclockconfig(void)
 
       putreg32(regval, STM32_RCC_DCKCFGR2);
 
-      /* Enable PLLI2S */
-
-      regval = getreg32(STM32_RCC_CR);
-      regval |= RCC_CR_PLLI2SON;
-      putreg32(regval, STM32_RCC_CR);
-
-      /* Wait until the PLLI2S is ready */
-
-      while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
-        {
-        }
-#endif
-
 #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
       /* Low speed internal clock source LSI */