arch/arm/src/stm32h7/stm32_sdmmc: check IDMA buffer address
For SDMMC1, IDMA cannot access SRAM123 or SRAM4. Refer to ST AN5200 for details. This patch makes stm32_dmapreflight check the buffer address and return an error when the buffer is located in a invalid address space. This does not fix the hardware limitation but at least makes it visible.
This commit is contained in:
Pierre-Olivier Vauboin
Abdelatif Guettouche
parent
369293dd84
commit
07bd520ccb
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@ -98,6 +98,12 @@
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* be monitored off the an HP work thread for a residual of less than
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* FIFO_SIZE_IN_BYTES / 2.
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*
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* HW Issues when using IDMA
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*
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* The DMA buffer must be located in a zone accessible via IDMA.
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* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. Refer to ST AN5200.
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* Buffer validity is checked when CONFIG_ARCH_HAVE_SDIO_PREFLIGHT is set.
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*
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* MDMA is only available on for SDMMC1 and Not supported at this time.
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*
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* Required system configuration options:
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@ -110,13 +116,13 @@
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* APIs to manage concurrent accesses on the SDMMC bus. This is not
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* needed for the simple case of a single SD card, for example.
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* CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA.
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* DMA support for SDMMC. If disabled disabled, the SDMMC will work in
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* DMA support for SDMMC. If disabled, the SDMMC will work in
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* interrupt mode and still use the IDMA to a local buffer for data
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* lengths less the 32 bytes due to the FIFO limitations.
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* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
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* operate with only a single data line (the default is to use all
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* 4 SD data lines).
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* CONFIG_CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug
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* CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug
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* output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
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* CONFIG_SDMMC1/2_SDIO_MODE
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* Build ins additional support needed only for SDIO cards (vs. SD memory
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@ -141,6 +147,11 @@
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#if !defined(CONFIG_STM32H7_SDMMC_IDMA)
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# warning "Large Non-DMA transfer may result in RX overrun failures"
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#elif defined(CONFIG_STM32H7_SDMMC1)
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# define SRAM123_START STM32_SRAM123_BASE
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# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE)
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# define SRAM4_START STM32_SRAM4_BASE
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# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE)
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#endif
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#ifndef CONFIG_SCHED_WORKQUEUE
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@ -153,7 +164,7 @@
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#endif
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#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES)
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# undef CONFIG_CONFIG_STM32H7_SDMMC_XFRDEBUG
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# undef CONFIG_STM32H7_SDMMC_XFRDEBUG
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#endif
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#ifdef CONFIG_SDMMC1_SDIO_PULLUP
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@ -1515,6 +1526,21 @@ static void stm32_endtransfer(struct stm32_dev_s *priv,
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sdmmc_putreg32(priv, STM32_SDMMC_XFRDONE_ICR, STM32_SDMMC_ICR_OFFSET);
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#if defined(CONFIG_STM32H7_SDMMC_IDMA) && \
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!defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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/* invalidate dcache in case of DMA receive. */
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if (priv->receivecnt)
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{
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up_invalidate_dcache((uintptr_t)priv->buffer,
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(uintptr_t)priv->buffer + priv->remaining);
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}
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#endif
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/* DMA debug instrumentation */
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stm32_sample(priv, SAMPLENDX_END_TRANSFER);
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/* Mark the transfer finished */
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priv->remaining = 0;
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@ -3038,7 +3064,29 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev,
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static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
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{
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/* DMA must be possible to the buffer */
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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/* IDMA must be possible to the buffer */
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#if defined(CONFIG_STM32H7_SDMMC1)
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if (priv->base == STM32_SDMMC1_BASE)
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{
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/* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. */
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if (((uintptr_t)buffer >= SRAM123_START &&
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(uintptr_t)buffer + buflen <= SRAM123_END) ||
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((uintptr_t)buffer >= SRAM4_START &&
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(uintptr_t)buffer + buflen <= SRAM4_END))
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{
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mcerr("invalid IDMA address "
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"buffer:0x%08x end:0x%08x\n",
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buffer, buffer + buflen - 1);
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return -EFAULT;
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}
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}
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#endif
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# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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/* buffer alignment is required for DMA transfers with dcache in buffered
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@ -3048,15 +3096,11 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
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* ARMV7M_DCACHE_LINESIZE boundaries.
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*/
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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if (buffer != priv->rxfifo &&
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(((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 ||
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((uintptr_t)(buffer + buflen) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0))
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{
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dmainfo("stm32_dmapreflight: dcache unaligned "
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mcerr("dcache unaligned "
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"buffer:0x%08x end:0x%08x\n",
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buffer, buffer + buflen - 1);
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return -EFAULT;
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@ -3276,7 +3320,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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static int stm32_dmadelydinvldt(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
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{
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/* Invaliate cache to physical memory when not in DTCM memory. */
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/* Invalidate cache to physical memory when not in DTCM memory. */
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if ((uintptr_t)buffer < DTCM_START ||
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(uintptr_t)buffer + buflen > DTCM_END)
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