SAMA5D4: Add missing mappings for the VDEC and L2CC memory regions

This commit is contained in:
Gregory Nutt 2014-06-21 14:25:47 -06:00
parent 942d24a005
commit 04e6fdf043
4 changed files with 23 additions and 2 deletions

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@ -56,6 +56,7 @@
/* These are bits maps of PIDs in the H64MX SPSELR registers. These are used by
* application code to quickly determine if a given PID is served by H32MX or H64MX
* which, in turn, is needed to know if the peripheral secured in SPSELR).
* Reference: "In Matrix" column of "Table 9-1. Peripheral identifiers."
*
* NOTE that these hard-code bit values must match the PID assignments in
* arch/arm/include/sama5/sama5*_irq.h.

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@ -254,12 +254,14 @@
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
#define SAM_VDEC_MMUFLAGS MMU_IOFLAGS
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPEHCI_MMUFLAGS MMU_IOFLAGS
#define SAM_AXIMX_MMUFLAGS MMU_IOFLAGS
#define SAM_DAP_MMUFLAGS MMU_IOFLAGS
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
#define SAM_L2CC_MMUFLAGS MMU_IOFLAGS
/* If the NFC is not being used, the NFC SRAM can be used as general purpose
* SRAM (cached). If the NFC is used, then the NFC SRAM should be treated

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@ -188,11 +188,21 @@ static const struct section_mapping_s section_mapping[] =
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS
},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS
},
#endif
#ifdef SAM_VDEC_PSECTION
/* If the memory map supports a video decoder (VDEC), then map it */
{ SAM_VDEC_PSECTION, SAM_VDEC_VSECTION,
SAM_VDEC_MMUFLAGS, SAM_VDEC_NSECTIONS
},
#endif
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS
},
@ -212,6 +222,14 @@ static const struct section_mapping_s section_mapping[] =
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS
},
#ifdef SAM_L2CC_PSECTION
/* If the memory map supports an L2 cache controller (L2CC), then map it */
{ SAM_L2CC_PSECTION, SAM_L2CC_VSECTION,
SAM_L2CC_MMUFLAGS, SAM_L2CC_NSECTIONS
},
#endif
/* SAMA5 CS0 External Memories */
#ifdef CONFIG_SAMA5_EBICS0

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@ -350,7 +350,7 @@ static void sam_aic_initialize(uintptr_t base)
* EOICR register.
*/
for (i = 0; i < 8 ; i++)
for (i = 0; i < 8; i++)
{
putreg32(AIC_EOICR_ENDIT, base + SAM_AIC_EOICR_OFFSET);
}