From 032c7f1ec98da6bda8732517a2680419674dedff Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Tue, 19 Mar 2019 10:43:32 -0600 Subject: [PATCH] arch/armv7-m: Make the default NVIC_VECTAB_TBLOFF_MASK safer. The base address of the new vector table must be aligned to the size of the vector table extended to the next larger power of 2. --- arch/arm/src/armv7-m/nvic.h | 7 ------ arch/arm/src/armv7-m/up_ramvec_initialize.c | 24 +++++++++++++++++++++ 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index b439a7b3eb..cd81f171fc 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -555,13 +555,6 @@ #define NVIC_SYSH_PRIORITY_PR15_SHIFT 24 #define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT) -/* Vector Table Offset Register (VECTAB). This mask seems to vary among - * ARMv7-M implementations. It may need to be redefined in some - * architecture-specific header file. - */ - -#define NVIC_VECTAB_TBLOFF_MASK (0xffffff80) - /* Application Interrupt and Reset Control Register (AIRCR) */ #define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */ diff --git a/arch/arm/src/armv7-m/up_ramvec_initialize.c b/arch/arm/src/armv7-m/up_ramvec_initialize.c index 4db7bb2be3..98fd16f32f 100644 --- a/arch/arm/src/armv7-m/up_ramvec_initialize.c +++ b/arch/arm/src/armv7-m/up_ramvec_initialize.c @@ -56,6 +56,30 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + +/* Vector Table Offset Register (VECTAB). This mask seems to vary among + * ARMv7-M implementations. It may need to be redefined in some + * architecture-specific header file. By default, the base address of the + * new vector table must be aligned to the size of the vector table extended + * to the next larger power of 2. + */ + +#ifndef NVIC_VECTAB_TBLOFF_MASK +# if ARMV7M_VECTAB_SIZE > 512 +# define NVIC_VECTAB_TBLOFF_MASK (0xffff000) +# elif ARMV7M_VECTAB_SIZE > 256 +# define NVIC_VECTAB_TBLOFF_MASK (0xffff800) +# elif ARMV7M_VECTAB_SIZE > 128 +# define NVIC_VECTAB_TBLOFF_MASK (0xffffc00) +# elif ARMV7M_VECTAB_SIZE > 64 +# define NVIC_VECTAB_TBLOFF_MASK (0xffffe00) +# elif ARMV7M_VECTAB_SIZE > 32 +# define NVIC_VECTAB_TBLOFF_MASK (0xfffff00) +# else +# define NVIC_VECTAB_TBLOFF_MASK (0xfffff80) +# endif +#endif + /* Alignment ****************************************************************/ /* Per the ARMv7M Architecture reference manual, the NVIC vector table * requires 7-bit address alignment (i.e, bits 0-6 of the address of the