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arch/armv7-m: Make the default NVIC_VECTAB_TBLOFF_MASK safer. The base address of the new vector table must be aligned to the size of the vector table extended to the next larger power of 2.

This commit is contained in:
Xiang Xiao 2019-03-19 10:43:32 -06:00 committed by Gregory Nutt
parent 64252a298f
commit 032c7f1ec9
2 changed files with 24 additions and 7 deletions
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7
arch/arm/src/armv7-m/nvic.h
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@ -555,13 +555,6 @@
#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* Vector Table Offset Register (VECTAB). This mask seems to vary among
* ARMv7-M implementations. It may need to be redefined in some
* architecture-specific header file.
*/
#define NVIC_VECTAB_TBLOFF_MASK (0xffffff80)
/* Application Interrupt and Reset Control Register (AIRCR) */
#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */

24
arch/arm/src/armv7-m/up_ramvec_initialize.c
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@ -56,6 +56,30 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Vector Table Offset Register (VECTAB). This mask seems to vary among
* ARMv7-M implementations. It may need to be redefined in some
* architecture-specific header file. By default, the base address of the
* new vector table must be aligned to the size of the vector table extended
* to the next larger power of 2.
*/
#ifndef NVIC_VECTAB_TBLOFF_MASK
# if ARMV7M_VECTAB_SIZE > 512
# define NVIC_VECTAB_TBLOFF_MASK (0xffff000)
# elif ARMV7M_VECTAB_SIZE > 256
# define NVIC_VECTAB_TBLOFF_MASK (0xffff800)
# elif ARMV7M_VECTAB_SIZE > 128
# define NVIC_VECTAB_TBLOFF_MASK (0xffffc00)
# elif ARMV7M_VECTAB_SIZE > 64
# define NVIC_VECTAB_TBLOFF_MASK (0xffffe00)
# elif ARMV7M_VECTAB_SIZE > 32
# define NVIC_VECTAB_TBLOFF_MASK (0xfffff00)
# else
# define NVIC_VECTAB_TBLOFF_MASK (0xfffff80)
# endif
#endif
/* Alignment ****************************************************************/
/* Per the ARMv7M Architecture reference manual, the NVIC vector table
* requires 7-bit address alignment (i.e, bits 0-6 of the address of the