From 002d4c40a4339d848a80fda2960bd161a09ae3a9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 13 Dec 2014 07:44:13 -0600 Subject: [PATCH] STM32 OTG HS DEV (in FS mode): Disable ULPI clock enable in RCC AHB1 Register. If Both ULPI and the FS clock enable bits are set in FS mode, then the ARM never awakens froom WFI due to a chip issue. From Ken Pettit --- arch/arm/src/stm32/stm32_otghsdev.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index c7e7fdadc4..d03e6c83cc 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -5309,6 +5309,16 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(0xbfffffff, STM32_OTGHS_GINTSTS); + /* Disable the ULPI Clock enable in RCC AHB1 Register. This must + * be done because if both the ULPI and the FS PHY clock enable bits + * are set at the same time, the ARM never awakens from WFI due to + * some bug / errata in the chip. + */ + + regval = stm32_getreg(STM32_RCC_AHB1LPENR); + regval &= ~RCC_AHB1ENR_OTGHSULPIEN; + stm32_putreg(regval, STM32_RCC_AHB1LPENR); + /* Enable the interrupts in the INTMSK */ regval = (OTGHS_GINT_RXFLVL | OTGHS_GINT_USBSUSP | OTGHS_GINT_ENUMDNE |