2016-03-26 04:21:24 +08:00
|
|
|
# CONFIG_ARCH_FPU is not set
|
2017-07-10 10:05:59 +08:00
|
|
|
# CONFIG_NSH_ARGCAT is not set
|
|
|
|
# CONFIG_NSH_CMDOPT_DF_H is not set
|
|
|
|
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
|
|
|
# CONFIG_NSH_CMDPARMS is not set
|
2016-03-26 04:21:24 +08:00
|
|
|
CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y
|
|
|
|
CONFIG_ARCH_BOARD="stm32l476vg-disco"
|
|
|
|
CONFIG_ARCH_BUTTONS=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_ARCH_CHIP_STM32L4=y
|
|
|
|
CONFIG_ARCH_CHIP_STM32L476RG=y
|
|
|
|
CONFIG_ARCH_INTERRUPTSTACK=2048
|
2016-03-31 03:48:36 +08:00
|
|
|
CONFIG_ARCH_IRQBUTTONS=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_ARCH_STACKDUMP=y
|
|
|
|
CONFIG_ARCH="arm"
|
|
|
|
CONFIG_BOARD_LOOPSPERMSEC=8499
|
2016-04-25 05:29:52 +08:00
|
|
|
CONFIG_BOARDCTL_IOCTL=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_BOARDCTL_UNIQUEID_SIZE=12
|
|
|
|
CONFIG_BOARDCTL_UNIQUEID=y
|
|
|
|
CONFIG_BUILTIN=y
|
2016-04-28 08:51:49 +08:00
|
|
|
CONFIG_DEV_LOOP=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_DEV_ZERO=y
|
|
|
|
CONFIG_DISABLE_POLL=y
|
|
|
|
CONFIG_EXAMPLES_ALARM=y
|
|
|
|
CONFIG_EXAMPLES_MEDIA=y
|
|
|
|
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
|
|
|
CONFIG_EXAMPLES_NSH=y
|
|
|
|
CONFIG_FS_PROCFS_REGISTER=y
|
|
|
|
CONFIG_FS_PROCFS=y
|
2016-05-04 00:09:23 +08:00
|
|
|
CONFIG_FS_ROMFS=y
|
|
|
|
CONFIG_FS_TMPFS=y
|
2016-03-26 04:21:24 +08:00
|
|
|
CONFIG_HAVE_CXX=y
|
|
|
|
CONFIG_HAVE_CXXINITIALIZE=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_INTELHEX_BINARY=y
|
|
|
|
CONFIG_MAX_TASKS=16
|
|
|
|
CONFIG_MAX_WDOGPARMS=2
|
|
|
|
CONFIG_MTD_N25QXXX=y
|
|
|
|
CONFIG_MTD_PARTITION=y
|
|
|
|
CONFIG_MTD=y
|
|
|
|
CONFIG_N25QXXX_SECTOR512=y
|
|
|
|
CONFIG_NFILE_DESCRIPTORS=8
|
|
|
|
CONFIG_NFILE_STREAMS=8
|
|
|
|
CONFIG_NSH_ARCHINIT=y
|
|
|
|
CONFIG_NSH_ARCHROMFS=y
|
2016-03-26 04:21:24 +08:00
|
|
|
CONFIG_NSH_BUILTIN_APPS=y
|
|
|
|
CONFIG_NSH_DISABLE_IFUPDOWN=y
|
|
|
|
CONFIG_NSH_FILEIOSIZE=512
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_NSH_LINELEN=64
|
|
|
|
CONFIG_NSH_READLINE=y
|
2016-05-04 00:09:23 +08:00
|
|
|
CONFIG_NSH_ROMFSETC=y
|
2017-07-10 10:05:59 +08:00
|
|
|
CONFIG_PREALLOC_MQ_MSGS=4
|
|
|
|
CONFIG_PREALLOC_TIMERS=4
|
|
|
|
CONFIG_PREALLOC_WDOGS=8
|
|
|
|
CONFIG_RAM_SIZE=98304
|
|
|
|
CONFIG_RAM_START=0x20000000
|
|
|
|
CONFIG_RAW_BINARY=y
|
|
|
|
CONFIG_RR_INTERVAL=200
|
|
|
|
CONFIG_RTC_ALARM=y
|
|
|
|
CONFIG_RTC_DATETIME=y
|
|
|
|
CONFIG_RTC_DRIVER=y
|
|
|
|
CONFIG_RTC_IOCTL=y
|
|
|
|
CONFIG_RTC_NALARMS=2
|
|
|
|
CONFIG_RTC=y
|
|
|
|
CONFIG_SCHED_WAITPID=y
|
|
|
|
CONFIG_SDCLONE_DISABLE=y
|
|
|
|
CONFIG_SPI=y
|
|
|
|
CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
|
|
|
|
CONFIG_STM32L4_DMA1=y
|
|
|
|
CONFIG_STM32L4_DMA2=y
|
|
|
|
CONFIG_STM32L4_PWR=y
|
|
|
|
CONFIG_STM32L4_QSPI=y
|
|
|
|
CONFIG_STM32L4_RNG=y
|
|
|
|
CONFIG_STM32L4_SAI1PLL=y
|
|
|
|
CONFIG_STM32L4_USART2=y
|
|
|
|
CONFIG_TASK_NAME_SIZE=0
|
|
|
|
CONFIG_USART2_SERIAL_CONSOLE=y
|
|
|
|
CONFIG_USER_ENTRYPOINT="nsh_main"
|
|
|
|
CONFIG_WDOG_INTRESERVE=1
|