2016-03-01 04:08:16 +08:00
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/****************************************************************************
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* arch/arm/include/imx6/chip.h
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*
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2021-03-21 04:46:19 +08:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-03-01 04:08:16 +08:00
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*
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2021-03-21 04:46:19 +08:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-03-01 04:08:16 +08:00
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*
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2021-03-21 04:46:19 +08:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-03-01 04:08:16 +08:00
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMX6_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMX6_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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2021-03-21 18:37:01 +08:00
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* Pre-processor Prototypes
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2016-03-01 04:08:16 +08:00
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****************************************************************************/
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2021-03-21 18:37:01 +08:00
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2016-03-02 04:15:43 +08:00
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/* The i.MX6 6Quad and 6Dual/DualLite are the only support i.MX6 family
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2016-03-03 00:28:09 +08:00
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* members. Individual differences between members of the families are not
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* accounted for.
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2016-03-02 04:15:43 +08:00
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*/
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2016-03-03 00:28:09 +08:00
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#if defined(CONFIG_ARCH_CHIP_IMX6_6QUAD)
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2016-03-05 08:43:16 +08:00
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# define IMX_OCRAM_SIZE (256*1024) /* Size of the On-Chip RAM (OCRAM) */
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# define IMX_L2CACHE_SIZE (1024*1024) /* 1MB L2 Cache */
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# define IMX_NXCPUS 4 /* Four CPUs */
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# define IMX_NGPU3D 1 /* One 3D graphics engine */
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# define IMX_N32SHADERS 4 /* Four 3D shaders */
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# define IMX_NGPU2D 2 /* Two 2D graphics engines */
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# define IMX_HAVE_DDR64 1 /* 64-bit DDR3 */
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# undef IMX_HAVE_DDR32 /* 32-bit DDR3 */
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# define IMX_HAVE_DDR32x2 1 /* Two channel 32-bit DDR3 */
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# define IMX_HAVE_SATAII 1 /* Integrated SATA-II */
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2020-02-23 16:50:23 +08:00
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# undef IMX_HAVE_EPD /* No integrated EPD controller */
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2016-03-03 00:28:09 +08:00
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#elif defined(CONFIG_ARCH_CHIP_IMX6_6DUAL)
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2016-03-05 08:43:16 +08:00
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# define IMX_OCRAM_SIZE (256*1024) /* Size of the On-Chip RAM (OCRAM) */
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# define IMX_L2CACHE_SIZE (1024*1024) /* 1MB L2 Cache */
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# define IMX_NXCPUS 2 /* Two CPUs */
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# define IMX_NGPU3D 1 /* One 3D graphics engine */
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# define IMX_N32SHADERS 4 /* Four 3D shaders */
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# define IMX_NGPU2D 2 /* Two 2D graphics engines */
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# define IMX_HAVE_DDR64 1 /* 64-bit DDR3 */
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# undef IMX_HAVE_DDR32 /* 32-bit DDR3 */
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# define IMX_HAVE_DDR32x2 1 /* Two channel 32-bit DDR3 */
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# define IMX_HAVE_SATAII 1 /* Integrated SATA-II */
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2020-02-23 16:50:23 +08:00
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# undef IMX_HAVE_EPD /* No integrated EPD controller */
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#elif defined(CONFIG_ARCH_CHIP_IMX6_6DUALLITE)
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# define IMX_OCRAM_SIZE (256*1024) /* Size of the On-Chip RAM (OCRAM) */
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# define IMX_L2CACHE_SIZE (512*1024) /* 512KB L2 Cache */
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# define IMX_NXCPUS 2 /* Two CPUs */
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# define IMX_NGPU3D 1 /* One 3D graphics engine */
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# define IMX_N32SHADERS 1 /* One 3D shaders */
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# define IMX_NGPU2D 1 /* One 2D graphics engine */
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# define IMX_HAVE_DDR64 1 /* 64-bit DDR3 */
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# undef IMX_HAVE_DDR32 /* No 32-bit DDR3 */
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# define IMX_HAVE_DDR32x2 1 /* Two channel 32-bit DDR3 */
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# undef IMX_HAVE_SATAII /* No integrated SATA-II */
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2020-02-23 16:50:23 +08:00
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# define IMX_HAVE_EPD 1 /* Integrated EPD controller */
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#elif defined(CONFIG_ARCH_CHIP_IMX6_6SOLO)
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# define IMX_OCRAM_SIZE (256*1024) /* Size of the On-Chip RAM (OCRAM) */
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# define IMX_L2CACHE_SIZE (512*1024) /* 512KB L2 Cache */
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# define IMX_NXCPUS 1 /* One CPU */
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# define IMX_NGPU3D 1 /* One 3D graphics engine */
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# define IMX_N32SHADERS 1 /* One 3D shaders */
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# define IMX_NGPU2D 1 /* One 2D graphics engine */
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# undef IMX_HAVE_DDR64 /* No 64-bit DDR3 */
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# define IMX_HAVE_DDR32 1 /* 32-bit DDR3 */
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# undef IMX_HAVE_DDR32x2 /* No two channel 32-bit DDR3 */
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# undef IMX_HAVE_SATAII /* No integrated SATA-II */
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2020-02-23 16:50:23 +08:00
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# define IMX_HAVE_EPD 1 /* Integrated EPD controller */
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2016-03-05 08:43:16 +08:00
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#elif defined(CONFIG_ARCH_CHIP_IMX6_6SOLOLITE)
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# define IMX_OCRAM_SIZE (256*1024) /* Size of the On-Chip RAM (OCRAM) */
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# define IMX_L2CACHE_SIZE (256*1024) /* 256KB L2 Cache */
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# define IMX_NXCPUS 1 /* One CPU */
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2016-03-05 08:44:30 +08:00
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# undef IMX_NGPU3D /* No 3D graphics engine */
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# define IMX_N32SHADERS 0 /* No 3D shaders */
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# define IMX_NGPU2D 1 /* One 2D graphics engine */
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# undef IMX_HAVE_DDR64 /* No 64-bit DDR3 */
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# define IMX_HAVE_DDR32 1 /* 32-bit DDR3 */
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# undef IMX_HAVE_DDR32x2 /* No two channel 32-bit DDR3 */
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# undef IMX_HAVE_SATAII /* No integrated SATA-II */
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2020-02-23 16:50:23 +08:00
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# define IMX_HAVE_EPD 1 /* Integrated EPD controller */
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2016-03-03 00:28:09 +08:00
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#else
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# error Unspecified i.MX6 chip
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#endif
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2016-03-01 04:08:16 +08:00
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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2021-03-21 18:37:01 +08:00
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* Public Functions Prototypes
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2016-03-01 04:08:16 +08:00
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_IMX6_CHIP_H */
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