2022-09-06 14:18:48 +08:00
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/****************************************************************************
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* arch/arm/include/gd32f4/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_GD32F4_CHIP_H
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#define __ARCH_ARM_INCLUDE_GD32F4_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Check the GD32F4 family configuration.
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* It must be done in arch/arm/src/gd32f4/Kconfig !
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*/
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2023-10-21 14:19:44 +08:00
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#if defined(CONFIG_ARCH_CHIP_GD32F450IK) || defined(CONFIG_ARCH_CHIP_GD32F470IK)
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# define GD32_NGPIO_PORTS 9 /* GPIOA-I */
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# define GD32_NCRC 1 /* CRC calculation unit */
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# define GD32_NTRNG 1 /* True random number generator (RNG) */
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# define GD32_NDMA 2 /* DMA0,1 */
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# define GD32_NIPA 1 /* Image processing accelerator */
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# define GD32_NIREF 1 /* Programmable current reference */
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# define GD32_NADC 3 /* 12-bit ADC0-2, 19 channels */
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# define GD32_NDAC 2 /* 12-bit DAC0,1 */
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# define GD32_NATIMER 2 /* Two advanced timers TIMER0 and 7 that support DMA */
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# define GD32_NGTIMER 4 /* 16-bit general timers TIMER2 and 3
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* 32-bit general timers TIMER1 and 4 that support DMA */
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# define GD32_NGTIMNDMA 6 /* 16-bit general timers TIMER8-13 that not support DMA */
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# define GD32_NBTIMER 2 /* Two basic timers, TIMER5,6 that support DMA */
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# define GD32_NUSART 8 /* USART0-2 and 5, UART 3,4 and 6,7 */
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# define GD32_NI2C 3 /* I2C0-2 */
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# define GD32_NSPI 6 /* SPI0-5 */
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# define GD32_NI2S 2 /* I2S1-2 (multiplexed with SPI1-2) */
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# define GD32_NDCI 1 /* Digital camera interface (DCI) */
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# define GD32_NTLI 1 /* TFT-LCD interface (TLI) */
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# define GD32_NSDIO 1 /* Secure digital input/output interface */
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# define GD32_NEXMC 1 /* External memory controller */
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# define GD32_NCAN 2 /* CAN0-1 */
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# define GD32_NETHERNET 1 /* 10/100 Ethernet MAC */
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# define GD32_NUSBFS 1 /* USB FS*/
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# define GD32_NUSBHS 1 /* USB HS*/
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2023-06-21 15:42:25 +08:00
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#elif defined(CONFIG_ARCH_CHIP_GD32F450ZK) || defined(CONFIG_ARCH_CHIP_GD32F470ZK)
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# define GD32_NGPIO_PORTS 8 /* GPIOA-H */
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# define GD32_NCRC 1 /* CRC calculation unit */
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# define GD32_NTRNG 1 /* True random number generator (RNG) */
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# define GD32_NDMA 2 /* DMA0,1 */
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# define GD32_NIPA 1 /* Image processing accelerator */
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# define GD32_NIREF 1 /* Programmable current reference */
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# define GD32_NADC 3 /* 12-bit ADC0-2, 19 channels */
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# define GD32_NDAC 2 /* 12-bit DAC0,1 */
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# define GD32_NATIMER 2 /* Two advanced timers TIMER0 and 7 that support DMA */
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# define GD32_NGTIMER 4 /* 16-bit general timers TIMER2 and 3
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* 32-bit general timers TIMER1 and 4 that support DMA */
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# define GD32_NGTIMNDMA 6 /* 16-bit general timers TIMER8-13 that not support DMA */
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# define GD32_NBTIMER 2 /* Two basic timers, TIMER5,6 that support DMA */
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# define GD32_NUSART 8 /* USART0-2 and 5, UART 3,4 and 6,7 */
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# define GD32_NI2C 3 /* I2C0-2 */
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# define GD32_NSPI 6 /* SPI0-5 */
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# define GD32_NI2S 2 /* I2S1-2 (multiplexed with SPI1-2) */
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# define GD32_NDCI 1 /* Digital camera interface (DCI) */
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# define GD32_NTLI 1 /* TFT-LCD interface (TLI) */
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# define GD32_NSDIO 1 /* Secure digital input/output interface */
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# define GD32_NEXMC 1 /* External memory controller */
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# define GD32_NCAN 2 /* CAN0-1 */
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# define GD32_NETHERNET 1 /* 10/100 Ethernet MAC */
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# define GD32_NUSBFS 1 /* USB FS*/
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# define GD32_NUSBHS 1 /* USB HS*/
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#else
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# error "Unknown GD32F4 chip type"
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#endif
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/* Get customizations for each supported chip and provide alternate function
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* pin-mapping
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*
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* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
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* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
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* particular pin-mapping will depend on the package and GD32 family. If
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* you are incorporating a new GD32 chip into NuttX, you will need to add
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* the pin-mapping to a header file and to include that header file below.
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* The chip-specific pin-mapping is defined in the chip datasheet.
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*/
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/* NVIC priority levels *****************************************************/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_GD32F4_CHIP_H */
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