164 lines
6.6 KiB
C
164 lines
6.6 KiB
C
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/****************************************************************************
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* arch/risc-v/include/thead/c9xx_csr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H
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#define __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* T-HEAD C9xx Machine Control and Status extension Registers */
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#define THEAD_CSR_MXSTATUS 0x7c0
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#define THEAD_CSR_MHCR 0x7c1
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#define THEAD_CSR_MCOR 0x7c2
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#define THEAD_CSR_MCCR2 0x7c3
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#define THEAD_CSR_MCER2 0x7c4
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#define THEAD_CSR_MHINT 0x7c5
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#define THEAD_CSR_MRMR 0x7c6
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#define THEAD_CSR_MRVBR 0x7c7
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#define THEAD_CSR_MCER 0x7c8
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#define THEAD_CSR_MCOUNTERWEN 0x7c9
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#define THEAD_CSR_MCOUNTERINTEN 0x7ca
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#define THEAD_CSR_MCOUNTEROF 0x7cb
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#define THEAD_CSR_MHINT2 0x7cc
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#define THEAD_CSR_MHINT3 0x7cd
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#define THEAD_CSR_MRADDR 0x7e0
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#define THEAD_CSR_MEXSTATUS 0x7e1
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#define THEAD_CSR_MNMICAUSE 0x7e2
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#define THEAD_CSR_MNMIPC 0x7e3
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#define THEAD_CSR_MHPMCR 0x7f0
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#define THEAD_CSR_MHPMSR 0x7f1
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#define THEAD_CSR_MHPMER 0x7f2
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#define THEAD_CSR_MTEECFG 0x7f4
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#define THEAD_CSR_MZONEID 0x7f5
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#define THEAD_CSR_ML2CPID 0x7f6
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#define THEAD_CSR_ML2WP 0x7f7
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#define THEAD_CSR_MDTCMCR 0x7f8
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#define THEAD_CSR_USP 0x7d1
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#define THEAD_CSR_MEICR 0x7d6
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#define THEAD_CSR_MEICR2 0x7d7
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#define THEAD_CSR_MBEADDR 0x7d8
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#define THEAD_CSR_MWMSR 0xfc2
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/* T-HEAD C9xx Machine Cache Access extension Registers */
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#define THEAD_CSR_MCINS 0x7d2
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#define THEAD_CSR_MCINDEX 0x7d3
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#define THEAD_CSR_MCDATA0 0x7d4
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#define THEAD_CSR_MCDATA1 0x7d5
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/* T-HEAD C9xx Machine CPU model extension Registers */
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#define THEAD_CSR_MCPUID 0xfc0
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#define THEAD_CSR_MAPBADDR 0xfc1
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/* T-HEAD C9xx Machine Multi-core extension Registers */
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#define THEAD_CSR_MSMPR 0x7f3
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/* T-HEAD C9xx Machine Debug Registers. */
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#define THEAD_CSR_MHALTCAUSE 0xfe0
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#define THEAD_CSR_MDBGINFO 0xfe1
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#define THEAD_CSR_MPCFIFO 0xfe2
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/* T-HEAD C9xx Supervisor Control and Status extension Registers */
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#define THEAD_CSR_SXSTATUS 0x5c0
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#define THEAD_CSR_SHCR 0x5c1
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#define THEAD_CSR_SCER2 0x5c2
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#define THEAD_CSR_SCER 0x5c3
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#define THEAD_CSR_SCOUNTERINTEN 0x5c4
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#define THEAD_CSR_SCOUNTEROF 0x5c5
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#define THEAD_CSR_SHINT 0x5c6
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#define THEAD_CSR_SHINT2 0x5c7
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#define THEAD_CSR_SHPMINHIBIT 0x5c8
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#define THEAD_CSR_SHPMCR 0x5c9
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#define THEAD_CSR_SHPMSR 0x5ca
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#define THEAD_CSR_SHPMER 0x5cb
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#define THEAD_CSR_SL2CPID 0x5cc
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#define THEAD_CSR_SL2WP 0x5cd
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#define THEAD_CSR_SBEADDR 0x5d0
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#define THEAD_CSR_SCYCLE 0x5e0
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#define THEAD_CSR_SINSTRET 0x5e2
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#define THEAD_CSR_SHPMCOUNTER1 0x5e1
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#define THEAD_CSR_SHPMCOUNTER2 0x5e2
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#define THEAD_CSR_SHPMCOUNTER3 0x5e3
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#define THEAD_CSR_SHPMCOUNTER4 0x5e4
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#define THEAD_CSR_SHPMCOUNTER5 0x5e5
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#define THEAD_CSR_SHPMCOUNTER6 0x5e6
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#define THEAD_CSR_SHPMCOUNTER7 0x5e7
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#define THEAD_CSR_SHPMCOUNTER8 0x5e8
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#define THEAD_CSR_SHPMCOUNTER9 0x5e9
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#define THEAD_CSR_SHPMCOUNTER10 0x5ea
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#define THEAD_CSR_SHPMCOUNTER11 0x5eb
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#define THEAD_CSR_SHPMCOUNTER12 0x5ec
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#define THEAD_CSR_SHPMCOUNTER13 0x5ed
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#define THEAD_CSR_SHPMCOUNTER14 0x5ee
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#define THEAD_CSR_SHPMCOUNTER15 0x5ef
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#define THEAD_CSR_SHPMCOUNTER16 0x5f0
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#define THEAD_CSR_SHPMCOUNTER17 0x5f1
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#define THEAD_CSR_SHPMCOUNTER18 0x5f2
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#define THEAD_CSR_SHPMCOUNTER19 0x5f3
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#define THEAD_CSR_SHPMCOUNTER20 0x5f4
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#define THEAD_CSR_SHPMCOUNTER21 0x5f5
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#define THEAD_CSR_SHPMCOUNTER22 0x5f6
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#define THEAD_CSR_SHPMCOUNTER23 0x5f7
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#define THEAD_CSR_SHPMCOUNTER24 0x5f8
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#define THEAD_CSR_SHPMCOUNTER25 0x5f9
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#define THEAD_CSR_SHPMCOUNTER26 0x5fa
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#define THEAD_CSR_SHPMCOUNTER27 0x5fb
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#define THEAD_CSR_SHPMCOUNTER28 0x5fc
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#define THEAD_CSR_SHPMCOUNTER29 0x5fd
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#define THEAD_CSR_SHPMCOUNTER30 0x5fe
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#define THEAD_CSR_SHPMCOUNTER31 0x5ff
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/* T-HEAD C9xx Supervisor MMU extension Registers */
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#define THEAD_CSR_SMIR 0x9c0
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#define THEAD_CSR_SMEL 0x9c1
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#define THEAD_CSR_SMEH 0x9c2
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#define THEAD_CSR_SMCIR 0x9c3
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/* T-HEAD C9xx User Floating-point control Registers. */
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#define THEAD_CSR_FXCR 0x800
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/* In mxstatus register */
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/* U-mode performance monitoring count enable */
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#define THEAD_MXSTATUS_PMDU (1 << 10)
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/* S-mode performance monitoring count enable */
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#define THEAD_MXSTATUS_PMDS (1 << 11)
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/* M-mode performance monitoring count enable */
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#define THEAD_MXSTATUS_PMDM (1 << 13)
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/* PMP minimum granularity control */
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#define THEAD_MXSTATUS_PMP4K (1 << 14)
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/* Misaligned access enable */
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#define THEAD_MXSTATUS_MM (1 << 15)
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/* Execute extended cache instructions in U-mode */
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#define THEAD_MXSTATUS_UCME (1 << 16)
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/* Clint timer/software interrupt supervisor extension enable */
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#define THEAD_MXSTATUS_CLINTEE (1 << 17)
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/* Disable hardware writeback */
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#define THEAD_MXSTATUS_MHRD (1 << 18)
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/* Disable Icache snoop D-Cache */
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#define THEAD_MXSTATUS_INSDE (1 << 19)
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/* Extend MMU address attribute */
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#define THEAD_MXSTATUS_MAEE (1 << 21)
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/* Enables extended instruction sets */
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#define THEAD_MXSTATUS_ISAEE (1 << 22)
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#endif /* __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H */
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