69 lines
3.3 KiB
C
69 lines
3.3 KiB
C
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/****************************************************************************
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* arch/arm/include/stm32wl5/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32WL5_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32WL5_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#if defined(CONFIG_STM32WL5_STM32WL5XXX)
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# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */
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# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L5 chip"
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#endif
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#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
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# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */
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# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */
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# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */
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# define STM32WL5_NRNG 1 /* Random number generator (RNG) */
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# define STM32WL5_NUSART 2 /* USART 1-2 */
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# define STM32WL5_NLPUART 1 /* LPUART 1 */
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# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */
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# define STM32WL5_NI2C 3 /* I2C1-3 */
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# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */
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# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */
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# define STM32WL5_NADC 1 /* ADC1 */
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# define STM32WL5_NDAC 1 /* DAC1 */
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# define STM32WL5_NCRC 1 /* CRC1 */
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# define STM32WL5_NCOMP 1 /* COMP1 */
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#endif /* CONFIG_STM32WL5_STM32WL5XXX */
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32WL5_CHIP_H */
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