2022-03-09 01:03:25 +08:00
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_ARCH_LEDS is not set
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# CONFIG_NSH_ARGCAT is not set
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# CONFIG_NSH_CMDOPT_HEXDUMP is not set
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CONFIG_ARCH="xtensa"
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CONFIG_ARCH_BOARD="esp32s3-devkit"
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2022-03-11 02:18:20 +08:00
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CONFIG_ARCH_BOARD_COMMON=y
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2022-03-09 01:03:25 +08:00
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CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
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CONFIG_ARCH_CHIP="esp32s3"
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CONFIG_ARCH_CHIP_ESP32S3=y
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CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
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CONFIG_ARCH_INTERRUPTSTACK=2048
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libc/machine/xtensa: make longjmp safe against context switch
In order to turn longjmp context-switch safe, it's necessary
to disable interrupts before modifying windowbase and windowstart.
Otherwise, after a context switch, windowstart and windowbase
would be different, leading to a wrongly set windowstart bit due to
longjmp writing it based on the windowbase before the context switch.
This corrupts the registers at the next window overflow reaching
that wrongly set bit.
*Background:*
This PR is related to an issue first observed on ESP-IDF
https://github.com/espressif/esp-idf/issues/5229 and it was, then,
checked on NuttX using a test application.
*The test application:*
To check if the problem affects ESP32, ESP32-S2 and ESP32-S3 on
NuttX, it was created an application based on:
https://en.cppreference.com/w/c/program/longjmp
The application creates 16 tasks (`#define NUMBER_OF_TASKS 16`)
that implements the following daemon:
```
static int setjmp_longjmp_daemon(int argc, char *argv[])
{
for (int i = 0; i < NUMBER_OF_TASKS * 2; i++)
{
jmp_buf env;
volatile int count = 0;
if (setjmp(env) != UINT16_MAX)
{
foo(&env, ++count);
}
}
sem_post(&g_sem);
return EXIT_SUCCESS;
}
```
The main function also initializes a semaphore to avoid application
exiting before tasks return successfully:
```
sem_init(&g_sem, 0, -NUMBER_OF_TASKS);
```
Finally, the round-robin interval was lowered to 1ms to raise the
chances of the longjmp being interrupted by a context switch
(`CONFIG_RR_INTERVAL=1).
This setup was able to reproduce the problem prior to this patch
being applied.
2022-11-22 02:04:32 +08:00
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CONFIG_ARCH_SETJMP_H=y
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2022-03-09 01:03:25 +08:00
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARCH_XTENSA=y
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CONFIG_BOARD_LOOPSPERMSEC=16717
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_ESP32S3_UART0=y
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CONFIG_FS_PROCFS=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_IDLETHREAD_STACKSIZE=3072
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INIT_STACKSIZE=3072
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CONFIG_INTELHEX_BINARY=y
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=114688
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CONFIG_RAM_START=0x20000000
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_WAITPID=y
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CONFIG_SMP=y
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CONFIG_SMP_NCPUS=2
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CONFIG_STACK_COLORATION=y
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CONFIG_START_DAY=8
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CONFIG_START_MONTH=3
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CONFIG_START_YEAR=2022
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2023-05-27 01:58:26 +08:00
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CONFIG_SYSLOG_BUFFER=y
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2022-03-09 01:03:25 +08:00
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CONFIG_SYSTEM_NSH=y
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CONFIG_TESTING_GETPRIME=y
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CONFIG_TESTING_OSTEST=y
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CONFIG_TESTING_SMP=y
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CONFIG_UART0_SERIAL_CONSOLE=y
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