2014-11-04 06:13:12 +08:00
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/****************************************************************************
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2019-08-08 04:49:39 +08:00
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* boards/arm/efm32/efm32gg-stk3700/include/board.h
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2014-11-04 06:13:12 +08:00
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*
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2021-03-18 01:14:12 +08:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2014-11-04 06:13:12 +08:00
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*
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2021-03-18 01:14:12 +08:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2014-11-04 06:13:12 +08:00
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*
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2021-03-18 01:14:12 +08:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2014-11-04 06:13:12 +08:00
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*
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****************************************************************************/
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2019-08-08 04:49:39 +08:00
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#ifndef __BOARDS_ARM_EFM32_EFM32GG_STK3700_INCLUDE_BOARD_H
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#define __BOARDS_ARM_EFM32_EFM32GG_STK3700_INCLUDE_BOARD_H
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2014-11-04 06:13:12 +08:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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2019-05-25 08:51:49 +08:00
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#include "hardware/efm32_cmu.h"
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#include "hardware/efm32_usart.h"
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2014-11-04 06:13:12 +08:00
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/****************************************************************************
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2015-04-08 23:15:17 +08:00
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* Pre-processor Definitions
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2014-11-04 06:13:12 +08:00
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****************************************************************************/
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2019-08-13 00:06:40 +08:00
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2014-11-04 06:13:12 +08:00
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/* Clocking *****************************************************************/
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2019-08-13 00:06:40 +08:00
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2014-11-04 06:13:12 +08:00
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/* Clock Sources
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* - 1-28 MHz High Frequency RC Oscillator (HFRCO)
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* - 4-32 MHz High Frequency Crystal Oscillator (HFXO)
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* - 32.768 kHz Low Frequency RC Oscillator (LFRCO)
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* - 32.768 kHz Low Frequency Crystal Oscillator (LFXO)
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* - 1KHz Ultra Low Frequency RC Oscillator (ULFRCO)
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*
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* The device boots with 14 MHz HFRCO as the HFCLK source.
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*/
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#define BOARD_HAVE_HFXO 1 /* Have High frequency crystal oscillator */
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#define BOARD_HAVE_LFXO 1 /* Have Loq frequency crystal oscillator */
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#define BOARD_HFRCO_FREQUENCY 14000000 /* 14MHz on reset */
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#define BOARD_HFXO_FREQUENCY 48000000 /* 48MHz crystal on board */
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#define BOARD_LFRCO_FREQUENCY 32768 /* Low frequency oscillator */
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#define BOARD_LFXO_FREQUENCY 32768 /* 32MHz crystal on board */
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#define BOARD_ULFRCO_FREQUNCY 1000 /* Ultra low frequency oscillator */
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/* HFCLK - High Frequency Clock
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*
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* HFCLK is the selected High Frequency Clock. This clock is used by the CMU
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* and drives the two prescalers that generate HFCORECLK and HFPERCLK. The
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* HFCLK can be driven by a high-frequency oscillator (HFRCO or HFXO) or one
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* of the low-frequency oscillators (LFRCO or LFXO). By default the HFRCO is
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* selected.
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*/
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#define BOARD_HFCLKSEL _CMU_CMD_HFCLKSEL_HFXO
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#define BOARD_HFCLKDIV 0 /* Does not apply to EFM32G */
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#define BOARD_HFCLK_FREQUENCY BOARD_HFXO_FREQUENCY
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/* HFCORECLK - High Frequency Core Clock
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*
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* HFCORECLK is a prescaled version of HFCLK. This clock drives the Core
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* Modules, which consists of the CPU and modules that are tightly coupled
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* to the CPU, e.g. MSC, DMA etc. The frequency of HFCORECLK is set using
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* the CMU_HFCORECLKDIV register.
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*/
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#define BOARD_HFCORECLKDIV _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT
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#define BOARD_HFCORECLK_FREQUENCY BOARD_HFXO_FREQUENCY
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/* HFPERCLK - High Frequency Peripheral Clock
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*
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* Like HFCORECLK, HFPERCLK can also be a prescaled version of HFCLK. This
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* clock drives the High-Frequency Peripherals. The frequency of HFPERCLK is
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* set using the CMU_HFPERCLKDIV register.
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*/
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#define BOARD_HFPERCLKDIV _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT
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#define BOARD_HFPERCLK_FREQUENCY BOARD_HFXO_FREQUENCY
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/* LFACLK - Low Frequency A Clock
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*
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* LFACLK is the selected clock for the Low Energy A Peripherals. There are
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* four selectable sources for LFACLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO.
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* From reset, the LFACLK source is set to LFRCO. However, note that the
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* LFRCO is disabled from reset. The selection is configured using the LFA
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* field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy A
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* Peripherals to be used as high-frequency peripherals.
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*
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* Use _CMU_LFCLKSEL_LFA_DISABLED to disable.
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* ULFRCO is a special case.
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*/
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#if BOARD_HAVE_LFXO
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# define BOARD_LFACLKSEL _CMU_LFCLKSEL_LFA_LFXO
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# undef BOARD_LFACLK_ULFRCO
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# define BOARD_LFACLK_FREQUENCY BOARD_LFXO_FREQUENCY
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#else
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# define BOARD_LFACLKSEL _CMU_LFCLKSEL_LFA_LFRCO
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# undef BOARD_LFACLK_ULFRCO
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# define BOARD_LFACLK_FREQUENCY BOARD_LFRCO_FREQUENCY
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#endif
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/* LFBCLK - Low Frequency B Clock
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*
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* LFBCLK is the selected clock for the Low Energy B Peripherals. There are
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* four selectable sources for LFBCLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO.
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* From reset, the LFBCLK source is set to LFRCO. However, note that the
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* LFRCO is disabled from reset. The selection is configured using the LFB
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* field in CMU_LFCLKSEL. The HFCORECLK/2 setting allows the Low Energy B
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* Peripherals to be used as high-frequency peripherals.
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*
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* Use _CMU_LFCLKSEL_LFA_DISABLED to disable.
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* ULFRCO is a special case.
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*/
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#define BOARD_LFBCLKSEL _CMU_LFCLKSEL_LFB_LFXO
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#undef BOARD_LFBCLK_ULFRCO
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#define BOARD_LFBCLK_FREQUENCY BOARD_LFXO_FREQUENCY
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/* PCNTnCLK - Pulse Counter n Clock
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*
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* Each available pulse counter is driven by its own clock, PCNTnCLK where
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* n is the pulse counter instance number. Each pulse counter can be
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* configured to use an external pin (PCNTn_S0) or LFACLK as PCNTnCLK.
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*/
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/* WDOGCLK - Watchdog Timer Clock
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*
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* The Watchdog Timer (WDOG) can be configured to use one of three different
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* clock sources: LFRCO, LFXO or ULFRCO. ULFRCO (Ultra Low Frequency RC
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* Oscillator) is a separate 1 kHz RC oscillator that also runs in EM3.
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*/
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/* AUXCLK - Auxiliary Clock
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*
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* AUXCLK is a 1-28 MHz clock driven by a separate RC oscillator, AUXHFRCO.
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* This clock is used for flash programming and Serial Wire Output (SWO).
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* During flash programming this clock will be active. If the AUXHFRCO has
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* not been enabled explicitly by software, the MSC will automatically
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* start and stop it. The AUXHFRCO is enabled by writing a 1 to AUXHFRCOEN
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* in CMU_OSCENCMD. This explicit enabling is required when SWO is used.
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*/
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/* LEDs *********************************************************************/
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2019-08-13 00:06:40 +08:00
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2014-11-04 06:13:12 +08:00
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/* The EFM32 Giant Gecko Start Kit has two yellow LEDs marked LED0 and LED1.
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* These LEDs are controlled by GPIO pins on the EFM32. The LEDs are
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* connected to pins PE2 and PE3 in an active high configuration:
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*
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* ------------------------------------- --------------------
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* EFM32 PIN BOARD SIGNALS
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* ------------------------------------- --------------------
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* E2/BCK_VOUT/EBI_A09 #0/ MCU_PE2 UIF_LED0
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* TIM3_CC2 #1/U1_TX #3/ACMP0_O #1
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* E3/BCK_STAT/EBI_A10 #0/U1_RX #3/ MCU_PE3 UIF_LED1
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* ACMP1_O #1
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* ------------------------------------- --------------------
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*
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* All LEDs are grounded and so are illuminated by outputting a high
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* value to the LED.
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*/
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2015-11-02 00:53:34 +08:00
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/* LED index values for use with board_userled() */
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2014-11-04 06:13:12 +08:00
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#define BOARD_LED0 0
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#define BOARD_LED1 1
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#define BOARD_NLEDS 2
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2015-11-02 00:53:34 +08:00
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/* LED bits for use with board_userled_all() */
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2014-11-04 06:13:12 +08:00
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#define BOARD_LED0_BIT (1 << BOARD_LED0)
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/efm32_autoleds.c. The LEDs are used to
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* encode OS-related events as follows:
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*
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* SYMBOL Val Meaning LED state
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* LED0 LED1
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2019-08-13 00:06:40 +08:00
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* ----------------- --- ----------------------- -------- --------
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*/
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2014-11-04 06:13:12 +08:00
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#define LED_STARTED 0 /* NuttX has been started OFF OFF */
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#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */
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#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */
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#define LED_STACKCREATED 1 /* Idle stack created ON OFF */
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#define LED_INIRQ 2 /* In an interrupt No change */
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#define LED_SIGNAL 2 /* In a signal handler No change */
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#define LED_ASSERTION 2 /* An assertion failed No change */
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#define LED_PANIC 3 /* The system has crashed OFF Blinking */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/* Buttons ******************************************************************/
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2019-08-13 00:06:40 +08:00
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2014-11-04 06:13:12 +08:00
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/* The EFM32 Giant Gecko Start Kit has two buttons marked PB0 and PB1. They
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* are connected to the EFM32, and are debounced by RC filters with a time
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* constant of 1ms. The buttons are connected to pins PB9 and PB10:
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*
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* ------------------------------------- --------------------
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* EFM32 PIN BOARD SIGNALS
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* ------------------------------------- --------------------
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* B9/EBI_A03/U1_TX #2 MCU_PB9 UIF_PB0
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* B10/EBI_A04/U1_RX #2 MCU_PB10 UIF_PB1
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* ------------------------------------- --------------------
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*
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* Buttons are connected to ground so they will read low when closed.
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*/
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#define BUTTON_PB0 0
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#define BUTTON_PB1 1
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#define NUM_BUTTONS 2
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#define BUTTON_PB0_BIT (1 << BUTTON_PB0)
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#define BUTTON_PB1_BIT (1 << BUTTON_PB1)
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/* Pin routing **************************************************************/
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2019-08-13 00:06:40 +08:00
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2014-11-04 06:13:12 +08:00
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/* UART0:
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*
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2014-11-04 07:20:03 +08:00
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* The kit contains a board controller that is responsible for performing
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* various board level tasks, such as handling the debugger and the Advanced
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* Energy Monitor. An interface is provided between the EFM32 and the board
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* controller in the form of a UART connection. The connection is enabled by
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* setting the EFM_BC_EN (PF7) line high, and using the lines EFM_BC_TX
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* (PE0) and EFM_BC_RX (PE1) for communicating.
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*
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* U0_TX #1 PE0 MCU_PE0, UART0_TX #0, EFM_BC_RX, BC_UART_RX
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* U0_RX #1 PE1 MCU_PE1, UART0_TX #1, EFM_BC_TX, BC_UART_TX
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2014-11-04 06:13:12 +08:00
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*/
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2014-11-13 02:50:09 +08:00
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#define BOARD_UART0_RX_GPIO (GPIO_PORTE|GPIO_PIN1)
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#define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0)
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#define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1
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2014-11-04 06:13:12 +08:00
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/* LEUART0:
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*
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2014-11-13 02:50:09 +08:00
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* LEU0_TX #0 PD4 Available on TP122 and EXP pin 12
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* LEU0_RX #0 PD5 Available on TP123 and EXP pin 14
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2014-11-04 06:13:12 +08:00
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*/
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2014-11-13 02:50:09 +08:00
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#define BOARD_LEUART0_RX_GPIO (GPIO_PORTD|GPIO_PIN5)
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#define BOARD_LEUART0_TX_GPIO (GPIO_PORTD|GPIO_PIN4)
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2014-11-04 07:20:03 +08:00
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#define BOARD_LEUART0_ROUTE_LOCATION _LEUART_ROUTE_LOCATION_LOC0
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2014-11-04 06:13:12 +08:00
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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2019-08-08 04:49:39 +08:00
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#endif /* __BOARDS_ARM_EFM32_EFM32GG_STK3700_INCLUDE_BOARD_H */
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