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incubator-nuttx/configs/esp32-core/scripts/esp32.cfg

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ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
#
Update README
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# Example configuration file to hook up an ESP32 module or board to a JTAG
ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
# adapter. Please modify this file to your local setup.
#
#
# Include the configuration for the JTAG adapter. We use the Tian TUMPA here.
Update README
2016-11-15 01:52:33 +08:00
# If you have a different interface, please edit this to include the
ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
# configuration file of yours.
Update README
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# source [find interface/ftdi/olimex-arm-usb-ocd.cfg]
ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
# The ESP32 only supports JTAG.
transport select jtag
# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
adapter_khz 200
# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and
# will do automatic RTOS detection. This can be be adjusted by uncommenting any of the
# following lines:
# Only configure the PRO CPU
#set ESP32_ONLYCPU 1
# Only configure the APP CPU
#set ESP32_ONLYCPU 2
# Disable RTOS support
set ESP32_RTOS none
# Force RTOS to be FreeRTOS
#set ESP32_RTOS FreeRTOS
#Source the ESP32 configuration file
source [find target/esp32.cfg]
# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
# chip runs at. When a hard reset happens (e.g. because someone switches the board off
# and on) the ESP32 will use the current TDI value as the bootstrap value because the
# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the
Update README
2016-11-15 01:52:33 +08:00
# bootstrapping. These lines basically set the idle value of the TDO line to a
ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
# specified value, therefore reducing the chance of a bad bootup due to a bad flash
# voltage greatly.
# Enable this for 1.8V SPI flash
ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...)
2016-12-14 22:15:03 +08:00
# esp108 flashbootstrap 1.8
ESP32 Core v2: Include a copy of the OpenOCD config file.
2016-11-15 01:30:40 +08:00
# Enable this for 3.3V SPI flash
ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...)
2016-12-14 22:15:03 +08:00
esp108 flashbootstrap 3.3