68 lines
1.9 KiB
Plaintext
68 lines
1.9 KiB
Plaintext
# Low Latency Pipeline and PCM
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#
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# Pipeline Endpoints for connection are :-
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#
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# host PCM_C <--B5-- volume(0C) <--B4-- source DAI0
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`pga.m4')
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include(`mixercontrol.m4')
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#
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# Controls
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#
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# Volume Mixer control with max value of 32
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C_CONTROLMIXER(PCM PCM_ID Capture Volume, PIPELINE_ID,
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CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
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CONTROLMIXER_MAX(, 40),
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false,
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CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3),
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Channel register and shift for Front Left/Right,
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LIST(` ', KCONTROL_CHANNEL(FL, 0, 0), KCONTROL_CHANNEL(FR, 0, 1)))
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#
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# Components and Buffers
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#
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# Host "Low Latency Capture" PCM
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# with 0 sink and 2 source periods
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W_PCM_CAPTURE(PCM_ID, Low Latency Capture, 0, 2, 0)
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# "Capture Volume" has 2 sink and source periods for host and DAI ping-pong
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W_PGA(0, PIPELINE_FORMAT, 2, 2, 0, LIST(` ', "PCM PCM_ID Capture Volume PIPELINE_ID"))
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# Capture Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_DAI_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_HOST_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM <--B1-- volume <--B0-- source DAI0
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P_GRAPH(pipe-ll-capture-PIPELINE_ID, PIPELINE_ID,
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LIST(` ',
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`dapm(Low Latency Capture PCM_ID, N_PCMC(PCM_ID))',
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`dapm(N_PCMC(PCM_ID), N_BUFFER(1))',
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`dapm(N_BUFFER(1), N_PGA(0))',
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`dapm(N_PGA(0), N_BUFFER(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(0))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Low Latency Capture PCM_ID)
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#
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# PCM Configuration
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#
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PCM_CAPABILITIES(Low Latency Capture PCM_ID, `S32_LE,S24_LE,S16_LE', 48000, 48000, 2, 4, 2, 4, 192, 16384, 65536, 65536)
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