75 lines
1.9 KiB
Plaintext
75 lines
1.9 KiB
Plaintext
# Capture EQ Pipeline and PCM
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#
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# Pipeline Endpoints for connection are :-
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#
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# host PCM_C <--- B1 <--- EQ_IIR 0 <-- B0 <-- sink DAI0
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`bytecontrol.m4')
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include(`eq_iir.m4')
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#
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# Controls
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#
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# Use 50 Hz highpass response with +20 dB gain
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include(`eq_iir_coef_highpass_50hz_20db_48khz.m4')
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# EQ Bytes control with max value of 255
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C_CONTROLBYTES(EQIIR, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
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CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 316),
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,
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EQIIR_priv)
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#
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# Components and Buffers
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#
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# Host "Highpass Capture" PCM
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# with 0 sink and 2 source periods
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W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2, 2)
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# "EQ 0" has 2 sink period and 2 source periods
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W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "EQIIR"))
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# Capture Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_PASS_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_PASS_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM_C <--- B1 <--- EQ_IIR 0 <-- B0 <-- sink DAI0
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P_GRAPH(pipe-pass-capture-PIPELINE_ID, PIPELINE_ID,
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LIST(` ',
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`dapm(Highpass Capture PCM_ID, N_PCMC(PCM_ID))',
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`dapm(N_PCMC(PCM_ID), N_BUFFER(1))',
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`dapm(N_BUFFER(1), N_EQ_IIR(0))',
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`dapm(N_EQ_IIR(0), N_BUFFER(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(0))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
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#
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# PCM Configuration
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#
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PCM_CAPABILITIES(Highpass Capture PCM_ID, COMP_FORMAT_NAME(PIPELINE_FORMAT), 48000, 48000, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
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