soft/topology/sof/pipe-eq-capture.m4

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# Capture EQ Pipeline and PCM
#
# Pipeline Endpoints for connection are :-
#
# host PCM_C <--- B1 <--- EQ_IIR 0 <-- B0 <-- sink DAI0
# Include topology builder
include(`utils.m4')
include(`buffer.m4')
include(`pcm.m4')
include(`dai.m4')
include(`pipeline.m4')
include(`bytecontrol.m4')
include(`eq_iir.m4')
#
# Controls
#
# Use 50 Hz highpass response with +20 dB gain
include(`eq_iir_coef_highpass_50hz_20db_48khz.m4')
# EQ Bytes control with max value of 255
C_CONTROLBYTES(EQIIR, PIPELINE_ID,
CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
, , ,
CONTROLBYTES_MAX(, 316),
,
EQIIR_priv)
#
# Components and Buffers
#
# Host "Highpass Capture" PCM
# with 0 sink and 2 source periods
W_PCM_CAPTURE(PCM_ID, Highpass Capture, 0, 2, 2)
# "EQ 0" has 2 sink period and 2 source periods
W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "EQIIR"))
# Capture Buffers
W_BUFFER(0, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_PASS_MEM_CAP)
W_BUFFER(1, COMP_BUFFER_SIZE(2,
COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
PLATFORM_PASS_MEM_CAP)
#
# Pipeline Graph
#
# host PCM_C <--- B1 <--- EQ_IIR 0 <-- B0 <-- sink DAI0
P_GRAPH(pipe-pass-capture-PIPELINE_ID, PIPELINE_ID,
LIST(` ',
`dapm(Highpass Capture PCM_ID, N_PCMC(PCM_ID))',
`dapm(N_PCMC(PCM_ID), N_BUFFER(1))',
`dapm(N_BUFFER(1), N_EQ_IIR(0))',
`dapm(N_EQ_IIR(0), N_BUFFER(0))'))
#
# Pipeline Source and Sinks
#
indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(0))
indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Highpass Capture PCM_ID)
#
# PCM Configuration
#
PCM_CAPABILITIES(Highpass Capture PCM_ID, COMP_FORMAT_NAME(PIPELINE_FORMAT), 48000, 48000, PIPELINE_CHANNELS, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)