100 lines
2.5 KiB
Plaintext
100 lines
2.5 KiB
Plaintext
#
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# Topology for generic Haswell board with no codec.
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`ssp.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Haswell DSP configuration
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include(`platform/intel/hsw.m4')
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#
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# Define the pipelines
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#
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# PCM0 ----> volume ---------------+
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# |--low latency mixer ----> volume ----> SSP2
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# PCM2 ----> SRC -----> volume ----+
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# |
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# Tone -----> volume ----+
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#
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# PCM1 <---- Volume <---- SSP0
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#
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4,
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1, 0, 2, s32le,
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48, 1000, 0, 0)
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# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
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2, 0, 2, s32le,
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48, 1000, 0, 0)
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# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le.
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# Schedule 192 frames per 4000us deadline on core 0 with priority 1
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PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4,
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3, 1, 2, s32le,
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192, 4000, 1, 0)
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# Tone Playback pipeline 5 using max 2 channels of s32le.
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# Schedule 192 frames per 4000us deadline on core 0 with priority 2
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PIPELINE_ADD(sof/pipe-tone.m4,
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5, 2, s32le,
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192, 4000, 2, 0)
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# Connect pipelines together
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SectionGraph."pipe-hsw-rt5640" {
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index "0"
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lines [
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# media 0
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_3)
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#tone
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_5)
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]
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}
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#
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# DAI configuration
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#
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# SSP port 0 is our only pipeline DAI
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#
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# playback DAI is SSP0 using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, SSP, 0, Codec,
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PIPELINE_SOURCE_1, 2, s24le,
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48, 1000, 0, 0)
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# capture DAI is SSP0 using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, SSP, 0, Codec,
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PIPELINE_SINK_2, 2, s24le,
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48, 1000, 0, 0)
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# PCM Low Latency
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PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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#
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# BE configurations - overrides config in ACPI if present
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#
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DAI_CONFIG(SSP, 0, 0, Codec,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, 0, 24)))
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