Topology: Add Equalizer
This patch adds EQ, bytecontrol, and EQ+volume pipeline m4 macros and an enhanced topology with EQ for UP2 + HiFiberry. There is not yet FIR/IIR type select. The EQ type is currently hardcoded into kernel. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com> Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
This commit is contained in:
Seppo Ingalsuo
Jaska Uimonen
parent
15030d4cab
commit
baa791f6e1
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@ -35,7 +35,8 @@ MACHINES = \
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sof-apl-wm8804.tplg \
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sof-apl-da7219.tplg \
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sof-glk-da7219.tplg \
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sof-icl-nocodec.tplg
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sof-icl-nocodec.tplg \
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sof-apl-eq-pcm512x.tplg
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# Uncomment the following line if you want to debug conf files
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.PRECIOUS: %.conf
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@ -71,4 +72,5 @@ EXTRA_DIST = \
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sof-apl-wm8804.m4 \
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sof-apl-da7219.m4 \
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sof-glk-da7219.m4 \
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sof-icl-nocodec.m4
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sof-icl-nocodec.m4 \
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sof-apl-eq-pcm512x.m4
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@ -0,0 +1,54 @@
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divert(-1)
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dnl Define macro for byte control
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dnl CONTROLBYTES_MAX(comment, value)
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define(`CONTROLBYTES_MAX',
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`#$1'
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` max STR($2)')
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dnl CONTROLMIXER_TLV(comment, value)
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define(`CONTROLBYTES_TLV',
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`#$1'
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` tlv STR($2)')
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dnl CONTROLMIXER_OPS(info, comment, get, put)
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define(`CONTROLBYTES_OPS',
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`ops."ctl" {'
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` info STR($1)'
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` #$2'
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` }')
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dnl CONTROLMIXER_OPS(info, comment, get, put)
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define(`CONTROLBYTES_EXTOPS',
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`extops."extctl" {'
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` #$1'
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` get STR($2)'
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` put STR($3)'
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` }')
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dnl C_CONTROLMIXER(name, index, ops, base, num_regs, mask, max, tlv)
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define(`C_CONTROLBYTES',
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`SectionControlBytes.STR($1) {'
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`'
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` # control belongs to this index group'
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` index STR($2)'
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`'
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` # control uses bespoke driver get/put/info ID for io ops'
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` $3'
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` # control uses bespoke driver get/put/info ID for ext ops'
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` $4'
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`'
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` base STR($5)'
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` num_regs STR($6)'
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` mask STR($7)'
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` $8'
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` $9'
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` access ['
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` tlv_write'
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` tlv_read'
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` tlv_callback'
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` ]'
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`}')
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divert(0)dnl
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@ -0,0 +1,43 @@
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divert(-1)
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dnl Define macro for Eq effect widget
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dnl EQ name)
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define(`N_EQ', `EQ'PIPELINE_ID`.'$1)
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dnl W_EQ(name, format, periods_sink, periods_source, preload, kcontrols_list)
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define(`W_EQ',
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`SectionVendorTuples."'N_EQ($1)`_tuples_w" {'
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` tokens "sof_comp_tokens"'
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` tuples."word" {'
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` SOF_TKN_COMP_PERIOD_SINK_COUNT' STR($3)
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` SOF_TKN_COMP_PERIOD_SOURCE_COUNT' STR($4)
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` SOF_TKN_COMP_PRELOAD_COUNT' STR($5)
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` }'
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`}'
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`SectionData."'N_EQ($1)`_data_w" {'
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` tuples "'N_EQ($1)`_tuples_w"'
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`}'
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`SectionVendorTuples."'N_EQ($1)`_tuples_str" {'
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` tokens "sof_comp_tokens"'
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` tuples."string" {'
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` SOF_TKN_COMP_FORMAT' STR($2)
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` }'
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`}'
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`SectionData."'N_EQ($1)`_data_str" {'
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` tuples "'N_EQ($1)`_tuples_str"'
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`}'
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`SectionWidget."'N_EQ($1)`" {'
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` index "'PIPELINE_ID`"'
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` type "effect"'
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` no_pm "true"'
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` data ['
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` "'N_EQ($1)`_data_w"'
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` "'N_EQ($1)`_data_str"'
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` ]'
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` bytes ['
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$6
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` ]'
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`}')
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divert(0)dnl
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@ -0,0 +1,55 @@
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#
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# Topology for generic Apollolake UP^2 with pcm512x codec.
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`ssp.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Apollolake DSP configuration
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include(`platform/intel/bxt.m4')
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#
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# Define the pipelines
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#
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# PCM0 ----> volume -----> SSP5 (pcm512x)
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#
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-eq-volume-playback.m4,
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1, 0, 2, s32le,
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48, 1000, 0, 0)
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#
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# DAIs configuration
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#
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# playback DAI is SSP5 using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, SSP, 5, SSP5-Codec,
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PIPELINE_SOURCE_1, 2, s24le,
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48, 1000, 0, 0)
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# PCM Low Latency, id 0
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PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1)
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#
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# BE configurations - overrides config in ACPI if present
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#
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DAI_CONFIG(SSP, 5, 0, SSP5-Codec,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
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SSP_CLOCK(bclk, 3072000, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(2, 32, 3, 3),
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SSP_CONFIG_DATA(SSP, 5, 24)))
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@ -0,0 +1,88 @@
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# Low Latency Passthrough with volume Pipeline and PCM
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#
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# Pipeline Endpoints for connection are :-
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#
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# host PCM_P --> B0 --> EQ 0 --> B1 --> Volume 0 --> B2 --> sink DAI0
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`pga.m4')
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include(`dai.m4')
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include(`mixercontrol.m4')
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include(`bytecontrol.m4')
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include(`pipeline.m4')
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include(`eq.m4')
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#
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# Controls
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#
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# Volume Mixer control with max value of 32
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C_CONTROLMIXER(Master Playback Volume, PIPELINE_ID,
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CONTROLMIXER_OPS(volsw, 256 binds the mixer control to volume get/put handlers, 256, 256),
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CONTROLMIXER_MAX(, 32),
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false,
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CONTROLMIXER_TLV(TLV 32 steps from -90dB to +6dB for 3dB, vtlv_m90s3),
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Channel register and shift for Front Left/Right,
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LIST(` ', KCONTROL_CHANNEL(FL, 1, 0), KCONTROL_CHANNEL(FR, 1, 1)))
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# EQ Bytes control with max value of 255
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C_CONTROLBYTES(EQ, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
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CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 10))
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#
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# Components and Buffers
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#
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# Host "Passthrough Playback" PCM
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# with 2 sink and 0 source periods
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W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, 2, 0, 2)
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# "Volume" has 2 source and 2 sink periods
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W_PGA(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "Master Playback Volume PIPELINE_ID"))
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# "EQ 0" has 2 sink period and 2 source periods
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W_EQ(0, PIPELINE_FORMAT, 2, 2, 2, LIST(` ', "EQ"))
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# Playback Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_HOST_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_HOST_MEM_CAP)
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W_BUFFER(2, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, SCHEDULE_FRAMES),
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PLATFORM_DAI_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM_P --> B0 --> EQ 0 --> B1 --> Volume 0 --> B2 --> sink DAI0
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P_GRAPH(pipe-pass-vol-playback-PIPELINE_ID, PIPELINE_ID,
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LIST(` ',
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`dapm(N_PCMP(PCM_ID), Passthrough Playback PCM_ID)',
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`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
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`dapm(N_EQ(0), N_BUFFER(0))',
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`dapm(N_BUFFER(1), N_EQ(0))',
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`dapm(N_PGA(0), N_BUFFER(1))',
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`dapm(N_BUFFER(2), N_PGA(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_ID)
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#
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# PCM Configuration
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#
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PCM_CAPABILITIES(Passthrough Playback PCM_ID, `S32_LE,S24_LE,S16_LE', 48000, 48000, 2, 8, 2, 16, 192, 16384, 65536, 65536)
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@ -0,0 +1,74 @@
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#
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# Topology for pass through pipeline
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#
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# Include topology builder
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include(`pipeline.m4')
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include(`dai.m4')
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include(`utils.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Baytrail DSP configuration
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include(`dsps/byt.m4')
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#
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# Machine Specific Config - !! MUST BE SET TO MATCH TEST MACHINE DRIVER !!
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#
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# TEST_PIPE_NAME - Pipe name
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# TEST_DAI_LINK_NAME - BE DAI link name e.g. "NoCodec"
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# TEST_SSP_PORT - SSP port number e.g. 2
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# TEST_SSP_FORMAT - SSP data format e.g s16le
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# TEST_PIPE_FORMAT - Pipeline format e.g. s16le
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# TEST_SSP_MCLK - SSP MCLK in Hz
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# TEST_SSP_BCLK - SSP BCLK in Hz
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# TEST_SSP_PHY_BITS - SSP physical slot size
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# TEST_SSP_DATA_BITS - SSP data slot size
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#
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#
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# Define the pipeline
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#
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# PCM0 <---> SSP TEST_SSP_PORT
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#
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# Passthrough playback pipeline 1 on PCM 0 using max 2 channels of s24le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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# Use DMAC 0 channel 1 for PCM audio playback data
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PIPELINE_PCM_DAI_ADD(sof/pipe-TEST_PIPE_NAME-playback.m4,
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1, 0, 2, TEST_PIPE_FORMAT,
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48, 1000, 0, 0, 0, 1,
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SSP, TEST_SSP_PORT, TEST_SSP_FORMAT, 2)
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#
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# DAI configuration
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#
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# SSP port TEST_SSP_PORT is our only pipeline DAI
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#
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# playback DAI is SSP TEST_SSP_PORT using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, SSP, TEST_SSP_PORT, TEST_DAI_LINK_NAME,
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PIPELINE_SOURCE_1, 2, TEST_SSP_FORMAT,
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48, 1000, 0, 0)
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# PCM Passthrough
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PCM_PLAYBACK_ADD(Passthrough, 3, 0, 0, PIPELINE_PCM_1)
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#
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# BE configurations - overrides config in ACPI if present
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#
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# Clocks masters wrt codec
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#
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# TEST_SSP_DATA_BITS bit I2S using TEST_SSP_PHY_BITS bit sample conatiner on SSP TEST_SSP_PORT
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#
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DAI_CONFIG(SSP, TEST_SSP_PORT, TEST_DAI_LINK_NAME, I2S, TEST_SSP_DATA_BITS,
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DAI_CLOCK(mclk, TEST_SSP_MCLK, slave),
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DAI_CLOCK(bclk, TEST_SSP_BCLK, slave),
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DAI_CLOCK(fsync, 48000, slave),
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DAI_TDM(2, TEST_SSP_PHY_BITS, 3, 3))
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