tplg: add nocodec topology for icelake

Signed-off-by: Rander Wang <rander.wang@linux.intel.com>

topology/Makefile.am

@@ -31,7 +31,8 @@ MACHINES = \
 	sof-hsw-rt5640.tplg \
 	sof-apl-tdf8532.tplg \
 	sof-apl-pcm512x.tplg \
-	sof-glk-codec.tplg
+	sof-glk-codec.tplg \
+	sof-icl-nocodec.tplg
 
 # Uncomment the following line if you want to debug conf files
 .PRECIOUS: %.conf

topology/platform/intel/icl.m4

@@ -0,0 +1,38 @@
+#
+# Icelake differentiation for pipelines and components
+#
+
+include(`memory.m4')
+
+dnl Memory capabilities for different buffer types on Icelake
+define(`PLATFORM_DAI_MEM_CAP',
+	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
+define(`PLATFORM_HOST_MEM_CAP',
+	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
+define(`PLATFORM_PASS_MEM_CAP',
+	MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
+define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))
+
+# Low Latency PCM Configuration
+W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens,
+		LIST(`		', `SOF_TKN_SCHED_MIPS	"50000"'))
+
+W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)
+
+# Media PCM Configuration
+W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens,
+		LIST(`		', `SOF_TKN_SCHED_MIPS	"100000"'))
+
+W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)
+
+# Tone Signal Generator Configuration
+W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens,
+		LIST(`		', `SOF_TKN_SCHED_MIPS	"200000"'))
+
+W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)
+
+# DAI schedule Configuration - scheduled by IRQ
+W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens,
+		LIST(`		', `SOF_TKN_SCHED_MIPS	"5000"'))
+
+W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)

topology/sof-icl-nocodec.m4

@@ -0,0 +1,71 @@
+#
+# Topology for generic Icelake board with nocodec
+#
+
+# Include topology builder
+include(`utils.m4')
+include(`dai.m4')
+include(`pipeline.m4')
+include(`ssp.m4')
+
+# Include TLV library
+include(`common/tlv.m4')
+
+# Include Token library
+include(`sof/tokens.m4')
+
+# Include Icelake DSP configuration
+include(`platform/intel/icl.m4')
+
+#
+# Define the pipelines
+#
+# PCM0 ----> Volume ----> SSP0
+#
+# PCM1 <---- Volume <---- SSP0
+#
+
+# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le.
+# Schedule 48 frames per 1000us deadline on core 0 with priority 0
+PIPELINE_PCM_DAI_ADD(sof/pipe-volume-playback.m4,
+	1, 0, 2, s24le,
+	48, 1000, 0, 0, SSP, 0, s24le, 2)
+
+# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le.
+# Schedule 48 frames per 1000us deadline on core 0 with priority 0
+PIPELINE_PCM_DAI_ADD(sof/pipe-volume-capture.m4,
+	2, 0, 2, s24le,
+	48, 1000, 0, 0, SSP, 0, s24le, 2)
+
+#
+# DAI configuration
+#
+# SSP port 0 is our only pipeline DAI
+#
+
+# playback DAI is SSP0 using 2 periods
+# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
+DAI_ADD(sof/pipe-dai-playback.m4,
+	1, SSP, 0, NoCodec-0,
+	PIPELINE_SOURCE_1, 2, s24le,
+	48, 1000, 0, 0)
+
+# capture DAI is SSP0 using 2 periods
+# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
+DAI_ADD(sof/pipe-dai-capture.m4,
+	2, SSP, 0, NoCodec-0,
+	PIPELINE_SINK_2, 2, s24le,
+	48, 1000, 0, 0)
+
+# PCM Low Latency
+PCM_DUPLEX_ADD(Passthrough, 3, 0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
+
+#
+# BE configurations - overrides config in ACPI if present
+#
+DAI_CONFIG(SSP, 0, 0, NoCodec-0,
+	   SSP_CONFIG(DSP_B, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
+		      SSP_CLOCK(bclk, 2400000, codec_slave),
+		      SSP_CLOCK(fsync, 48000, codec_slave),
+		      SSP_TDM(2, 25, 3, 3),
+		      SSP_CONFIG_DATA(SSP, 0, 24)))