From 5452897dc9308c7e4fd4e17649550dec880eacdb Mon Sep 17 00:00:00 2001
From: Curtis Malainey <cujomalainey@google.com>
Date: Thu, 15 Nov 2018 18:32:29 -0800
Subject: [PATCH] update sof-apl-tdf8532

consolidate graph styles

Signed-off-by: Curtis Malainey <cujomalainey@google.com>
---
 topology/sof-apl-tdf8532.m4 | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/topology/sof-apl-tdf8532.m4 b/topology/sof-apl-tdf8532.m4
index c82c1f0..b8d1faa 100644
--- a/topology/sof-apl-tdf8532.m4
+++ b/topology/sof-apl-tdf8532.m4
@@ -20,16 +20,12 @@ include(`platform/intel/bxt.m4')
 #
 # Define the pipelines
 #
-# PCM0 ----> volume -----> SSP4
-# PCM1 ----> volume -----> SSP2(Dirana Pb)
-#      <---- Volume <----- SSP2(Dirana Cp)
-# PCM2 ----> volume -----> SSP0(BT HFP out)
-#      <---- volume <----- SSP0(BT HFP in)
-# PCM3 <---- Volume <----- SSP1(HDMI in)
-# PCM4 ----> volume -----> SSP3(Modem out)
-#      <---- volume <----- SSP3(Modem in)
-# PCM5 ----> volume -----> SSP5(TestPin out)
-#      <---- volume <----- SSP3(TestPin in)
+# PCM0 -----> Volume -----> SSP4
+# PCM1 <----> Volume <----> SSP2(Dirana Pb/Cp)
+# PCM2 <----> Volume <----> SSP0(BT HFP out/in)
+# PCM3 <----- Volume <----- SSP1(HDMI in)
+# PCM4 <----> Volume <----> SSP3(Modem out/in)
+# PCM5 <----> Volume <----> SSP5(TestPin out/in)
 #
 
 # Low Latency playback pipeline 1 on PCM 0 using max 4 channels of s32le.