From 26c9709f2df11909446fa46f61f436265a2dab5b Mon Sep 17 00:00:00 2001 From: Mengdong Lin Date: Thu, 2 Aug 2018 17:13:19 -0400 Subject: [PATCH] topology: Create HDA only m4 file for APL This patch creates sof_apl_hda.m4 to create topology for HDA only FE and BE links. Signed-off-by: Mengdong Lin --- topology/Makefile.am | 2 + topology/sof-apl-hda.m4 | 93 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 topology/sof-apl-hda.m4 diff --git a/topology/Makefile.am b/topology/Makefile.am index 6a03d48..7d2e82c 100644 --- a/topology/Makefile.am +++ b/topology/Makefile.am @@ -19,6 +19,7 @@ DEPS = \ MACHINES = \ sof-cht-nocodec.tplg \ sof-cht-max98090.tplg \ + sof-apl-hda.tplg \ sof-apl-nocodec.tplg \ sof-byt-nocodec.tplg \ sof-bdw-rt286.tplg \ @@ -53,6 +54,7 @@ clean-local: EXTRA_DIST = \ sof-cht-nocodec.m4 \ sof-cht-max98090.m4 \ + sof-apl-hda.m4 \ sof-apl-nocodec.m4 \ sof-byt-nocodec.m4 \ sof-bdw-rt286.m4 \ diff --git a/topology/sof-apl-hda.m4 b/topology/sof-apl-hda.m4 new file mode 100644 index 0000000..9fe9f3c --- /dev/null +++ b/topology/sof-apl-hda.m4 @@ -0,0 +1,93 @@ +# +# Topology for generic Apollolake board with no codec. +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`ssp.m4') +include(`pipeline.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include Apollolake DSP configuration +include(`platform/intel/bxt.m4') + +# +# Define the pipelines +# +# PCM0 ----> volume -----> iDisp1 +# PCM1 ----> Volume <----- iDisp2 +# PCM2 ----> volume -----> iDisp3 + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl frames, deadline, priority, core) + +# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s16le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 1, 0, 2, s16le, + 48, 1000, 0, 0) + +# Low Latency playback pipeline 3 on PCM 1 using max 2 channels of s16le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 3, 1, 2, s16le, + 48, 1000, 0, 0) + +# Low Latency playback pipeline 5 on PCM 2 using max 2 channels of s16le. +# Schedule 48 frames per 1000us deadline on core 0 with priority 0 +PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, + 5, 2, 2, s16le, + 48, 1000, 0, 0) + +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl frames, deadline, priority, core) + +# playback DAI is iDisp1 using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, HDA, 0, iDisp1, + PIPELINE_SOURCE_1, 2, s16le, + 48, 1000, 0, 0) + +# playback DAI is iDisp2 using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 3, HDA, 1, iDisp2, + PIPELINE_SOURCE_3, 2, s16le, + 48, 1000, 0, 0) + +# playback DAI is iDisp3 using 2 periods +# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 5, HDA, 2, iDisp3, + PIPELINE_SOURCE_5, 2, s16le, + 48, 1000, 0, 0) + + +dnl PCM_PLAYBACK_ADD(name, pcm_id, playback) +PCM_PLAYBACK_ADD(Port0, 0, PIPELINE_PCM_1) +PCM_PLAYBACK_ADD(Port1, 1, PIPELINE_PCM_3) +PCM_PLAYBACK_ADD(Port2, 2, PIPELINE_PCM_5) + +# +# BE configurations - overrides config in ACPI if present +# + +dnl HDA_DAI_CONFIG(dai_index, link_id, name) +HDA_DAI_CONFIG(0, 0, iDisp1) +HDA_DAI_CONFIG(1, 1, iDisp2) +HDA_DAI_CONFIG(2, 2, iDisp3) +