mirror of https://github.com/thesofproject/sof.git
85 lines
2.6 KiB
Plaintext
85 lines
2.6 KiB
Plaintext
#
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# Icelake differentiation for pipelines and components
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#
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include(`memory.m4')
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dnl Memory capabilities for different buffer types on Icelake
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define(`PLATFORM_DAI_MEM_CAP',
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MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
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define(`PLATFORM_HOST_MEM_CAP',
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MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
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define(`PLATFORM_PASS_MEM_CAP',
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MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE, MEM_CAP_HP))
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define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))
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# Low Latency PCM Configuration
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W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens,
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LIST(` ', `SOF_TKN_SCHED_MIPS "50000"'))
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W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)
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# Media PCM Configuration
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W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens,
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LIST(` ', `SOF_TKN_SCHED_MIPS "100000"'))
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W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)
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# Tone Signal Generator Configuration
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W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens,
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LIST(` ', `SOF_TKN_SCHED_MIPS "200000"'))
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W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)
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# DAI schedule Configuration - scheduled by IRQ
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W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens,
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LIST(` ', `SOF_TKN_SCHED_MIPS "5000"'))
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W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)
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#SSP setting for ICL platform
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undefine(`SSP_INDEX')
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define(`SSP_INDEX', 0)
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undefine(`SSP_NAME')
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define(`SSP_NAME', `SSP0-Codec')
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undefine(`SSP_MCLK_RATE')
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define(`SSP_MCLK_RATE', `19200000')
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#--------- SSP1 --------------
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#SSP setting for CML platform
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define(`SSP1_INDEX', 1)
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define(`SSP1_NAME', `SSP1-Codec')
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define(`SSP1_MCLK_RATE', `24000000')
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ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1',
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define(`SSP1_VALID_BITS', 24),
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define(`SSP1_VALID_BITS', 16))
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# playback DAI is SSP1 using 2 periods
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# Buffers use s16le format, with 48 frame per 1000us on core 0 with priority 0
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# With m/n divider available we can support 24 bit playback
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ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1',
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define(`SSP1_VALID_BITS_STR', s24le),
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define(`SSP1_VALID_BITS_STR', s16le))
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ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1',
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define(`SSP1_BCLK', 2304000),
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define(`SSP1_BCLK', 1500000))
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ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1',
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define(`SSP1_FSYNC', 48000),
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define(`SSP1_FSYNC', 46875))
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#SSP 1 (ID: 6)
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#Use BCLK delay in SSP_CONFIG_DATA only on supporting version
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ifelse(SOF_ABI_VERSION_3_9_OR_GRT, `1',
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define(`SET_SSP1_CONFIG_DATA', SSP_CONFIG_DATA(SSP, 1, SSP1_VALID_BITS, 0, 0, 10)),
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define(`SET_SSP1_CONFIG_DATA', SSP_CONFIG_DATA(SSP, 1, SSP1_VALID_BITS)))
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include(`platform/intel/dmic.m4')
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