mirror of https://github.com/thesofproject/sof.git
357 lines
12 KiB
Plaintext
357 lines
12 KiB
Plaintext
#
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# Topology for generic Cannonlake board with no codec and digital mic array.
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`ssp.m4')
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include(`pipeline.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include DSP configuration
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include(`platform/intel/'PLATFORM`.m4')
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# bxt has 2 cores but currently only one is enabled in the build
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ifelse(PLATFORM, `bxt', `define(NCORES, 1)')
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ifelse(PLATFORM, `cnl', `define(NCORES, 4)')
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ifelse(PLATFORM, `cml', `define(NCORES, 4)')
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ifelse(PLATFORM, `icl', `define(NCORES, 4)')
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ifelse(PLATFORM, `jsl', `define(NCORES, 2)')
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ifelse(PLATFORM, `tgl', `define(NCORES, 4)')
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ifelse(PLATFORM, `ehl', `define(NCORES, 4)')
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ifelse(PLATFORM, `adl', `define(NCORES, 4)')
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define(CHANNELS, `4')
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define(DMIC_PCM_48k_ID, `10')
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define(DMIC_PCM_16k_ID, `11')
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define(DMIC_PIPELINE_48k_ID, `20')
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define(DMIC_PIPELINE_16k_ID, `21')
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define(DMIC_DAI_LINK_48k_NAME, `NoCodec-3')
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define(DMIC_DAI_LINK_16k_NAME, `NoCodec-4')
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define(DMIC_DAI_LINK_48k_ID, `3')
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define(DMIC_DAI_LINK_16k_ID, `4')
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define(DMICPROC, `eq-iir-volume')
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define(DMIC16KPROC, `eq-iir-volume')
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define(DMICPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_48khz.m4')
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define(DMIC16KPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_16khz.m4')
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ifelse(NCORES, `4',
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`
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define(DMIC_48k_CORE_ID, `0')
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define(DMIC_16k_CORE_ID, `0')
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define(SSP0_CORE_ID, `0')
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define(SSP1_CORE_ID, `0')
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define(SSP2_CORE_ID, `0')
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')
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ifelse(NCORES, `2',
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`
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define(DMIC_48k_CORE_ID, `0')
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define(DMIC_16k_CORE_ID, `0')
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define(SSP0_CORE_ID, `0')
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define(SSP1_CORE_ID, `0')
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define(SSP2_CORE_ID, `0')
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')
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ifelse(NCORES, `1',
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`
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define(DMIC_48k_CORE_ID, `0')
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define(DMIC_16k_CORE_ID, `0')
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define(SSP0_CORE_ID, `0')
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define(SSP1_CORE_ID, `0')
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define(SSP2_CORE_ID, `0')
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')
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include(`platform/intel/intel-generic-dmic.m4')
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ifelse(PLATFORM, `bxt',
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`
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define(SSP0_IDX, `0')
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define(SSP1_IDX, `1')
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define(SSP2_IDX, `5')
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',
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`
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define(SSP0_IDX, `0')
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define(SSP1_IDX, `1')
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define(SSP2_IDX, `2')
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')
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define(PIPE_BITS, `s32le')
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define(DAI_BITS, `s24le')
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#
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# Define the pipelines
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#
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# PCM0 ---> Volume -----\
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# Mixer ----> SSP0
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# PCM3 ---> Volume -----/
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# PCM1 ---> Volume ----> Mixer ----> SSP1
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# PCM2 ---> volume ----> Mixer ----> SSP2
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#
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# SSP0 ---> Volume ----> PCM0
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# SSP1 ---> Volume ----> PCM1
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# SSP2 ---> Volume ----> PCM2
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# DMIC0 --> IIR -------> PCM10
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# DMIC1 --> IIR -------> PCM11
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#
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl period, priority, core,
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dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
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dnl time_domain, sched_comp)
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# Volume switch capture pipeline 2 on PCM 0 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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2, 0, 2, PIPE_BITS,
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1000, 0, SSP0_CORE_ID,
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48000, 48000, 48000)
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# Volume switch capture pipeline 4 on PCM 1 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP1_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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4, 1, 2, PIPE_BITS,
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1000, 0, SSP1_CORE_ID,
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48000, 48000, 48000)
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# Volume switch capture pipeline 6 on PCM 2 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline with priority 0 on core SSP2_CORE_ID
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PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4,
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6, 2, 2, PIPE_BITS,
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1000, 0, SSP2_CORE_ID,
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48000, 48000, 48000)
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#
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# DAIs configuration
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#
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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# playback DAI is SSP0 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP0_CORE_ID
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# The 'NOT_USED_IGNORED' is due to dependencies and is adjusted later with an explicit dapm line.
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DAI_ADD(sof/pipe-mixer-volume-dai-playback.m4,
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1, SSP, SSP0_IDX, NoCodec-0,
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NOT_USED_IGNORED, 2, DAI_BITS,
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1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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7, 0, 2, PIPE_BITS,
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1000, 0, SSP0_CORE_ID,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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# Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP0_CORE_ID with priority 0.
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# TODO: Modify pipeline deadline to account for deep buffering
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ifelse(PLATFORM, `bxt', `',
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`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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11, 3, 2, PIPE_BITS,
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1000, 0, SSP0_CORE_ID,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)')
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# capture DAI is SSP0 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP0_IDX
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, SSP, SSP0_IDX, NoCodec-0,
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PIPELINE_SINK_2, 2, DAI_BITS,
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1000, 0, SSP0_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is SSP1 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP1_CORE_ID
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DAI_ADD(sof/pipe-mixer-volume-dai-playback.m4,
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3, SSP, SSP1_IDX, NoCodec-1,
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NOT_USED_IGNORED, 2, DAI_BITS,
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1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 8 on PCM 1 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP1_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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8, 1, 2, PIPE_BITS,
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1000, 0, SSP1_CORE_ID,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_3)
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# capture DAI is SSP1 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP1_CORE_ID
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DAI_ADD(sof/pipe-dai-capture.m4,
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4, SSP, SSP1_IDX, NoCodec-1,
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PIPELINE_SINK_4, 2, DAI_BITS,
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1000, 0, SSP1_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is SSP2 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP2_CORE_ID
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DAI_ADD(sof/pipe-mixer-volume-dai-playback.m4,
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5, SSP, SSP2_IDX, NoCodec-2,
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NOT_USED_IGNORED, 2, DAI_BITS,
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1000, 0, SSP2_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# Low Latency playback pipeline 9 on PCM 2 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP2_CORE_ID with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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9, 2, 2, PIPE_BITS,
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1000, 0, SSP2_CORE_ID,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_5)
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# Deep buffer playback pipeline 11 on PCM 3 using max 2 channels of PIPE_BITS.
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# Set 1000us deadline on core SSP2_CORE_ID with priority 0.
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# TODO: Modify pipeline deadline to account for deep buffering
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ifelse(PLATFORM, `bxt',
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`PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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11, 3, 2, PIPE_BITS,
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1000, 0, SSP2_CORE_ID,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_5)')
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# capture DAI is SSP2 using 2 periods
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# Buffers use DAI_BITS format, 1000us deadline with priority 0 on core SSP2_CORE_ID
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DAI_ADD(sof/pipe-dai-capture.m4,
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6, SSP, SSP2_IDX, NoCodec-2,
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PIPELINE_SINK_6, 2, DAI_BITS,
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1000, 0, SSP2_CORE_ID, SCHEDULE_TIME_DOMAIN_TIMER)
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SectionGraph."mixer-host" {
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index "0"
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lines [
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# connect mixer dai pipelines to PCM pipelines
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_7)
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dapm(PIPELINE_MIXER_3, PIPELINE_SOURCE_8)
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dapm(PIPELINE_MIXER_5, PIPELINE_SOURCE_9)
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ifelse(PLATFORM, `bxt',
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`dapm(PIPELINE_MIXER_5, PIPELINE_SOURCE_11)',
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`dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_11)')
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]
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}
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dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
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PCM_DUPLEX_ADD(`Port'SSP0_IDX, 0, PIPELINE_PCM_7, PIPELINE_PCM_2)
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PCM_DUPLEX_ADD(`Port'SSP1_IDX, 1, PIPELINE_PCM_8, PIPELINE_PCM_4)
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PCM_DUPLEX_ADD(`Port'SSP2_IDX, 2, PIPELINE_PCM_9, PIPELINE_PCM_6)
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ifelse(PLATFORM,`bxt',
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`PCM_PLAYBACK_ADD(`Port'SSP2_IDX` Deep Buffer', 3, PIPELINE_PCM_11)',
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`PCM_PLAYBACK_ADD(`Port'SSP0_IDX` Deep Buffer', 3, PIPELINE_PCM_11)')
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#
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# BE configurations - overrides config in ACPI if present
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#
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ifelse(PLATFORM, `bxt', `define(ROOT_CLK, 19_2)')
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ifelse(PLATFORM, `cnl', `define(ROOT_CLK, 24)')
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ifelse(PLATFORM, `cml', `define(ROOT_CLK, 24)')
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ifelse(PLATFORM, `icl', `define(ROOT_CLK, 38_4)')
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ifelse(PLATFORM, `jsl', `define(ROOT_CLK, 38_4)')
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ifelse(PLATFORM, `tgl', `define(ROOT_CLK, 38_4)')
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ifelse(PLATFORM, `ehl', `define(ROOT_CLK, 38_4)')
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ifelse(PLATFORM, `adl', `define(ROOT_CLK, 38_4)')
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ifelse(ROOT_CLK, `19_2',
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`
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DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
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SSP_CLOCK(bclk, 3072000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 32, 3, 3),
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dnl SSP_CONFIG_DATA(type, idx, valid bits, mclk_id, quirks, bclk_delay,
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dnl clks_control, pulse_width, padding)
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SSP_CONFIG_DATA(SSP, SSP0_IDX, 32, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
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SSP_CLOCK(bclk, 3072000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 32, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP1_IDX, 32, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in),
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SSP_CLOCK(bclk, 3072000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 32, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP2_IDX, 32, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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')
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ifelse(ROOT_CLK, `24',
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`
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DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
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dnl SSP_CONFIG(format, mclk, bclk, fsync, tdm, ssp_config_data)
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
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SSP_CLOCK(bclk, 4800000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
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SSP_CLOCK(bclk, 4800000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in),
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SSP_CLOCK(bclk, 4800000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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')
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ifelse(ROOT_CLK, `38_4',
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`
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DAI_CONFIG(SSP, SSP0_IDX, 0, NoCodec-0,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP0_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP1_IDX, 1, NoCodec-1,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP1_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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DAI_CONFIG(SSP, SSP2_IDX, 2, NoCodec-2,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 38400000, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_consumer),
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SSP_CLOCK(fsync, 48000, codec_consumer),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, SSP2_IDX, 24, 0, SSP_QUIRK_LBM, 0,
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eval(SSP_CC_MCLK_ES | SSP_CC_BCLK_ES))))
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')
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