mirror of https://github.com/thesofproject/sof.git
301 lines
6.7 KiB
C
301 lines
6.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright(c) 2020 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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#include <sof/init.h>
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#include <rtos/idc.h>
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#include <rtos/interrupt.h>
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#include <sof/drivers/interrupt-map.h>
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#include <sof/lib/dma.h>
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#include <sof/schedule/schedule.h>
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#include <platform/drivers/interrupt.h>
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#include <platform/lib/memory.h>
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#include <sof/platform.h>
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#include <sof/lib/notifier.h>
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#include <sof/lib/pm_runtime.h>
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#include <sof/audio/pipeline.h>
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#include <sof/audio/component_ext.h>
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#include <sof/trace/trace.h>
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#include <rtos/wait.h>
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#include <rtos/clk.h>
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/* Zephyr includes */
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/pm/policy.h>
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#include <version.h>
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#include <zephyr/sys/__assert.h>
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#include <soc.h>
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LOG_MODULE_REGISTER(zephyr, CONFIG_SOF_LOG_LEVEL);
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extern K_KERNEL_STACK_ARRAY_DEFINE(z_interrupt_stacks, CONFIG_MP_NUM_CPUS,
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CONFIG_ISR_STACK_SIZE);
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/* 300aaad4-45d2-8313-25d0-5e1d6086cdd1 */
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DECLARE_SOF_RT_UUID("zephyr", zephyr_uuid, 0x300aaad4, 0x45d2, 0x8313,
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0x25, 0xd0, 0x5e, 0x1d, 0x60, 0x86, 0xcd, 0xd1);
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DECLARE_TR_CTX(zephyr_tr, SOF_UUID(zephyr_uuid), LOG_LEVEL_INFO);
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/*
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* Interrupts.
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*
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* Mostly mapped. Still needs some linkage symbols that can be removed later.
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*/
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/* needed for linkage only */
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const char irq_name_level2[] = "level2";
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const char irq_name_level5[] = "level5";
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/* imx currently has no IRQ driver in Zephyr so we force to xtos IRQ */
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#if defined(CONFIG_IMX)
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int interrupt_register(uint32_t irq, void(*handler)(void *arg), void *arg)
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{
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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return arch_irq_connect_dynamic(irq, 0, (void (*)(const void *))handler,
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arg, 0);
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#else
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tr_err(&zephyr_tr, "Cannot register handler for IRQ %u: dynamic IRQs are disabled",
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irq);
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return -EOPNOTSUPP;
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#endif
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}
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/* unregister an IRQ handler - matches on IRQ number and data ptr */
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void interrupt_unregister(uint32_t irq, const void *arg)
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{
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/*
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* There is no "unregister" (or "disconnect") for
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* interrupts in Zephyr.
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*/
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irq_disable(irq);
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}
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/* enable an interrupt source - IRQ needs mapped to Zephyr,
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* arg is used to match.
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*/
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uint32_t interrupt_enable(uint32_t irq, void *arg)
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{
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irq_enable(irq);
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return 0;
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}
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/* disable interrupt */
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uint32_t interrupt_disable(uint32_t irq, void *arg)
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{
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irq_disable(irq);
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return 0;
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}
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#endif
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/*
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* i.MX uses the IRQ_STEER
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*/
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#if !CONFIG_IMX
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void interrupt_mask(uint32_t irq, unsigned int cpu)
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{
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/* TODO: how do we mask on other cores with Zephyr APIs */
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}
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void interrupt_unmask(uint32_t irq, unsigned int cpu)
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{
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/* TODO: how do we unmask on other cores with Zephyr APIs */
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}
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void platform_interrupt_set(uint32_t irq)
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{
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/* handled by zephyr - needed for linkage */
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}
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void platform_interrupt_clear(uint32_t irq, uint32_t mask)
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{
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/* handled by zephyr - needed for linkage */
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}
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#endif
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/*
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* Notifier.
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*
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* Use SOF inter component messaging today. Zephyr has similar APIs that will
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* need some minor feature updates prior to merge. i.e. FW to host messages.
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* TODO: align with Zephyr API when ready.
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*/
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static struct notify *host_notify[CONFIG_CORE_COUNT];
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struct notify **arch_notify_get(void)
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{
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return host_notify + cpu_get_id();
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}
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/*
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* Debug
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*/
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void arch_dump_regs_a(void *dump_buf)
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{
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/* needed for linkage only */
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}
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/*
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* Xtensa. TODO: this needs removed and fixed in SOF.
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*/
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unsigned int _xtos_ints_off(unsigned int mask)
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{
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/* turn all local IRQs OFF */
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irq_lock();
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return 0;
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}
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/* Zephyr redefines log_message() and mtrace_printf() which leaves
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* totally empty the .static_log_entries ELF sections for the
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* sof-logger. This makes smex fail. Define at least one such section to
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* fix the build when sof-logger is not used.
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*/
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static inline const void *smex_placeholder_f(void)
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{
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_DECLARE_LOG_ENTRY(LOG_LEVEL_DEBUG,
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"placeholder so .static_log.X are not all empty",
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_TRACE_INV_CLASS, 0);
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return &log_entry;
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}
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/* Need to actually use the function and export something otherwise the
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* compiler optimizes everything away.
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*/
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const void *_smex_placeholder;
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int task_main_start(struct sof *sof)
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{
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_smex_placeholder = smex_placeholder_f();
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/* init default audio components */
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sys_comp_init(sof);
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/* init pipeline position offsets */
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pipeline_posn_init(sof);
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return 0;
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}
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int start_complete(void)
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{
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#if defined(CONFIG_IMX)
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#define SOF_IPC_QUEUED_DOMAIN SOF_SCHEDULE_LL_DMA
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#else
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#define SOF_IPC_QUEUED_DOMAIN SOF_SCHEDULE_LL_TIMER
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#endif
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/*
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* called from primary_core_init(), track state here
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* (only called from single core, no RMW lock)
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*/
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__ASSERT_NO_MSG(cpu_get_id() == PLATFORM_PRIMARY_CORE_ID);
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#if defined(CONFIG_PM)
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pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES);
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pm_policy_state_lock_get(PM_STATE_SOFT_OFF, PM_ALL_SUBSTATES);
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#endif
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/* let host know DSP boot is complete */
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return platform_boot_complete(0);
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}
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/*
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* Timestamps.
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*
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* TODO: move to generic code in SOF, currently platform code.
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*/
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/* get timestamp for host stream DMA position */
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void platform_host_timestamp(struct comp_dev *host,
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struct sof_ipc_stream_posn *posn)
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{
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int err;
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/* get host position */
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err = comp_position(host, posn);
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if (err == 0)
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posn->flags |= SOF_TIME_HOST_VALID;
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}
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/* get timestamp for DAI stream DMA position */
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void platform_dai_timestamp(struct comp_dev *dai,
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struct sof_ipc_stream_posn *posn)
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{
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int err;
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/* get DAI position */
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err = comp_position(dai, posn);
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if (err == 0)
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posn->flags |= SOF_TIME_DAI_VALID;
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/* get SSP wallclock - DAI sets this to stream start value */
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posn->wallclock = sof_cycle_get_64() - posn->wallclock;
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posn->wallclock_hz = clock_get_freq(PLATFORM_DEFAULT_CLOCK);
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posn->flags |= SOF_TIME_WALL_VALID;
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}
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/* get current wallclock for componnent */
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void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
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{
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*wallclock = sof_cycle_get_64();
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}
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/*
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* Multicore
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*
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* Mostly empty today waiting pending Zephyr CAVS SMP integration.
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*/
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#if CONFIG_MULTICORE && CONFIG_SMP
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static struct idc idc[CONFIG_MP_NUM_CPUS];
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static struct idc *p_idc[CONFIG_MP_NUM_CPUS];
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struct idc **idc_get(void)
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{
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int cpu = cpu_get_id();
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p_idc[cpu] = idc + cpu;
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return p_idc + cpu;
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}
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#endif
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#define DEFAULT_TRY_TIMES 8
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int poll_for_register_delay(uint32_t reg, uint32_t mask,
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uint32_t val, uint64_t us)
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{
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uint64_t tick = k_us_to_cyc_ceil64(us);
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uint32_t tries = DEFAULT_TRY_TIMES;
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uint64_t delta = tick / tries;
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if (!delta) {
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/*
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* If we want to wait for less than DEFAULT_TRY_TIMES ticks then
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* delta has to be set to 1 and number of tries to that of number
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* of ticks.
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*/
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delta = 1;
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tries = tick;
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}
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while ((io_reg_read(reg) & mask) != val) {
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if (!tries--) {
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LOG_DBG("poll timeout reg %u mask %u val %u us %u",
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reg, mask, val, (uint32_t)us);
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return -EIO;
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}
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wait_delay(delta);
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}
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return 0;
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}
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