mirror of https://github.com/thesofproject/sof.git
208 lines
5.8 KiB
Plaintext
208 lines
5.8 KiB
Plaintext
#
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# Topology for Icelake with rt700 codec.
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#
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# if XPROC is not defined, define with default pipe
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ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)')
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ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)')
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`alh.m4')
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include(`hda.m4')
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include(`platform/intel/dmic.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Icelake DSP configuration
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include(`platform/intel/icl.m4')
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# Define pipeline id for intel-generic-dmic.m4
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# to generate dmic setting
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ifelse(CHANNELS, `0', ,
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`
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define(DMIC_PCM_48k_ID, `10')
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define(DMIC_PIPELINE_48k_ID, `3')
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define(DMIC_DAI_LINK_48k_ID, `2')
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define(DMIC_PCM_16k_ID, `11')
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define(DMIC_PIPELINE_16k_ID, `4')
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define(DMIC_DAI_LINK_16k_ID, `3')
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include(`platform/intel/intel-generic-dmic.m4')
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'
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)
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DEBUG_START
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#
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# Define the pipelines
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#
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# PCM0 ---> volume ----> mixer --->ALH 2 BE dailink 0
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# PCM31 ---> volume ------^
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# PCM1 <--- volume <---- ALH 3 BE dailink 1
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# PCM10 <---------------- DMIC01 (dmic0 capture, BE dailink 2)
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# PCM11 <---------------- DMIC16k (dmic16k, BE dailink 3)
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# PCM5 ----> volume -----> iDisp1 (HDMI/DP playback, BE link 4)
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# PCM6 ----> volume -----> iDisp2 (HDMI/DP playback, BE link 5)
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# PCM7 ----> volume -----> iDisp3 (HDMI/DP playback, BE link 6)
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#
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dnl PIPELINE_PCM_ADD(pipeline,
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dnl pipe id, pcm, max channels, format,
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dnl period, priority, core,
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dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
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dnl time_domain, sched_comp)
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# Low Latency capture pipeline 2 on PCM 1 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline with priority 0 on core 0
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PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
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2, 1, 2, s24le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 6 on PCM 5 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline with priority 0 on core 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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6, 5, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 7 on PCM 6 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline with priority 0 on core 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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7, 6, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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# Low Latency playback pipeline 8 on PCM 7 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline with priority 0 on core 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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8, 7, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000)
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#
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# DAIs configuration
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#
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dnl DAI_ADD(pipeline,
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dnl pipe id, dai type, dai_index, dai_be,
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dnl buffer, periods, format,
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dnl deadline, priority, core, time_domain)
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# playback DAI is ALH(SDW0 PIN2) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-mixer-volume-dai-playback.m4,
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1, ALH, 2, SDW0-Playback,
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NOT_USED_IGNORED, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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# capture DAI is ALH(SDW0 PIN2) using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, ALH, 3, SDW0-Capture,
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PIPELINE_SINK_2, 2, s24le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# Low Latency playback pipeline 30 on PCM 0 using max 2 channels of s32le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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30, 0, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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# Deep buffer playback pipeline 31 on PCM 31 using max 2 channels of s32le
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# Set 1000us deadline on core 0 with priority 0.
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# TODO: Modify pipeline deadline to account for deep buffering
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ifdef(`HEADSET_DEEP_BUFFER',
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`
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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31, 31, 2, s32le,
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1000, 0, 0,
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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'
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)
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SectionGraph."mixer-host" {
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index "0"
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lines [
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# connect mixer dai pipelines to PCM pipelines
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_30)
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ifdef(`HEADSET_DEEP_BUFFER',
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`
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_31)
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'
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)
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]
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}
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# playback DAI is iDisp1 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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6, HDA, 0, iDisp1,
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PIPELINE_SOURCE_6, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp2 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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7, HDA, 1, iDisp2,
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PIPELINE_SOURCE_7, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# playback DAI is iDisp3 using 2 periods
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# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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8, HDA, 2, iDisp3,
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PIPELINE_SOURCE_8, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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# PCM Low Latency, id 0
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dnl PCM_PLAYBACK_ADD(name, pcm_id, playback)
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PCM_PLAYBACK_ADD(Jack Out, 0, PIPELINE_PCM_30)
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ifdef(`HEADSET_DEEP_BUFFER',
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`
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PCM_PLAYBACK_ADD(Jack Out DeepBuffer, 31, PIPELINE_PCM_31)
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'
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)
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PCM_CAPTURE_ADD(Jack In, 1, PIPELINE_PCM_2)
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PCM_PLAYBACK_ADD(HDMI 1, 5, PIPELINE_PCM_6)
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PCM_PLAYBACK_ADD(HDMI 2, 6, PIPELINE_PCM_7)
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PCM_PLAYBACK_ADD(HDMI 3, 7, PIPELINE_PCM_8)
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#
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# BE configurations - overrides config in ACPI if present
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#
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#ALH dai index = ((link_id << 8) | PDI id)
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#ALH SDW0 Pin2 (ID: 0)
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DAI_CONFIG(ALH, 2, 0, SDW0-Playback,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, 2, 48000, 2)))
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#ALH SDW0 Pin3 (ID: 1)
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DAI_CONFIG(ALH, 3, 1, SDW0-Capture,
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ALH_CONFIG(ALH_CONFIG_DATA(ALH, 3, 48000, 2)))
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# 3 HDMI/DP outputs (ID: 4,5,6)
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DAI_CONFIG(HDA, 0, 4, iDisp1,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2)))
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DAI_CONFIG(HDA, 1, 5, iDisp2,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2)))
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DAI_CONFIG(HDA, 2, 6, iDisp3,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 2, 48000, 2)))
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DEBUG_END
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