Commit Graph

13 Commits

Author SHA1 Message Date
Marc Herbert 19d2fbb625 west.yml: remove self.path: sof
The intent was to stop people from cloning the sof manifest git repo
under a different name than "sof". It did not work, I had to help
multiple people who did it anyway.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-11-09 14:15:07 +00:00
Kai Vehmanen a0d9a4e4ac west.yml: upgrade Zephyr to 2e66fac6d3ff
Total of 946 commits, including following related to
intel_adsp/sparse/dmic/xtensa:

728506df6f45 soc: intel_adsp/ace: wait for lpsram power up
7e0c1a81cb54 soc: intel_adsp/ace: remove z_delay from hpsram init
e3e24b266d2d soc: xtensa: intel_adsp: ace: Fix build when CONFIG_MP_NUM_CPUS=1
dbc366918d8f tests: Enable qemu_xtensa logging tests
2dc9257ae1ae drivers: dmic: remove invalid assert on dmic->created
a574957c7457 soc: xtensa: intel_adsp: ace: set number of cpus at boot
7ffc6c31b555 samples/boards: Add intel_adsp/code_relocation sample
e98a748ad24e soc/xtensa/intel_adsp/cavs: Support for code relocation
06990e69d676 soc/xtensa/intel_adsp/cavs: Expose linker script on include
8ac6f74a7de5 arch/xtensa: Enable code relocation
fb26f18ae1c3 soc/xtensa/sample_controller: Expose linker script on include
d7f46136e013 soc/xtensa: Use standard __data_start/__data_end markers
f5dc229bc5df drivers: wifi: esp32: add softap config
dd1c88d54862 dts: xtensa: intel: fix alh base addr for cavs25
1f6d6deaef44 sparse: fix sparse warnings found in sof compilation
af5fb91a6c1f soc: intel_adsp: ipc: Do not send message until previous one is acked
0a7c25e649d1 drivers: timer: intel_adsp: Update driver to use dts Kconfig symbol
b953ff1418d2 drivers: dmic: enable dmic mono configuration
bedc2e7ab436 drivers: dmic: remove soft_reset from dmic init flow
39c2007b04ec drivers: dmic: update dmic flow initialization
ba0617417a1d tests: intel_adsp: smoke: Convert CONFIG_MP_NUM_CPUS handling
f8fba49a4102 soc: xtensa: intel_adsp: Convert CONFIG_MP_NUM_CPUS handling
0ce0f43b36bd soc: xtensa: esp32: Convert CONFIG_MP_NUM_CPUS handling
9387d8689b32 soc: xtensa: esp32: Add CONFIG_SMP protection
ad05e795986f intel_adsp: mem_window: fix definition of memory windows
f09a3a1bd675 linker: intel_adsp: discard GNU-stack notes
5760fcc8ab42 soc: xtensa: esp32_net:
b09973c460e3 soc: intel_adsp/common: remove reference to hp_sram_pm_banks
a2cb4a7ce3b9 soc: intel_adsp/ace: always inline funcs to get memory bank cnt
3ffe2654268a soc: intel_adsp/common: only memcpy segment if needed
195db14400f2 soc: intel_adsp/ace: zero out memory at ram init

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-11-08 17:58:09 +02:00
Kwasowiec, Fabiola cd2c44389f west.yml: upgrade rimage to 3ee717eebc
upgrade rimage to
3ee717eebc

3ee717eebc probe: mtl.toml invaliv probe type
1f4a36e21f mux: fix module type
dcfd11bc4d mux: add mux cfg to list of modules
d957e0368b rimage: make ace15 signing to support openssl3
a1b6e6db33 manifest: add fw_ver_micro to manifest
fb28357912 config: mtl: add probe module

Signed-off-by: Kwasowiec, Fabiola <fabiola.kwasowiec@intel.com>
2022-10-20 11:09:53 +02:00
Marc Herbert 8fd351ea9a west.yml: add warning to keep git submodules in sync
Trying avoid out-of-sync situations like commit a3b3c525d1 ("west:
update to newer rimage baseline").

Also explain why sof cannot be cloned as "sof2"

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-10-13 10:47:49 -07:00
Kai Vehmanen 5702939836 west.yml: upgrade Zephyr to ed661a6c6909
Upgrade Zephyr from 0956647aaf6bd2b1e840adcc86db503f274d84a9 to
ed661a6c6909b338035b026cfc101ddda65ab8eb (1020 commits, including
441 since v3.2.0 tag).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-10-13 14:55:26 +03:00
Peter Ujfalusi a3b3c525d1 west: update to newer rimage baseline
tgl-h zephyr build is broken due to outdated rimage revision.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2022-09-27 17:19:15 +01:00
Marc Herbert 3d69a7f69e .github: extend yamllint line-length to 100
Also run on west.yml

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-09-26 12:33:56 +01:00
Kai Vehmanen d525235e0e west.yml: upgrade Zephyr to 3.2.0-rc1 level
Update Zephyr to 0956647aaf6bd2b1e840adcc86db503f274d84a9 (3.2.0-rc1
plus a few fixes merged to upstreamed after the tag).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-09-15 13:54:24 +01:00
Kai Vehmanen b965236529 west: update to newer Zephyr baseline
Update zephyr to commit dcda3eab8df7 ("tests: net: socket: tcp: move to
new ztest API").

Needed to bring in support for Intel mtrace logging backend.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-31 10:33:46 +01:00
Kai Vehmanen 5fb1d45562 west: update to newer Zephyr baseline
Update zephyr to commit 8e55e59c5917 ('arch: introduce config DCLS').

Fixes build errors due to missing core-isa.h with tgl Intel target with
gcc build chain.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-05 15:52:45 +01:00
Marc Herbert dfaf9b8f28 west.yml: clarify warning about ignored zephyr/west.yml changes
Fixes commit 2c9772d5ad ("Add west.yml configuring zephyr
dependencies from sof")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-08-04 09:46:22 +01:00
Andrey Borisovich 70406a0db0 scripts: added versioning to xtensa-build-zephyr.py and west manifest
Added versioning to scripts/xtensa-build-zephyr.py to get version
information when incompatible changes are done to the script.
Added yml schema version number to west.yml manifest.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-08-03 11:43:22 +01:00
Krzysztof Frydryk 2c9772d5ad Add west.yml configuring zephyr dependencies from sof
Added west.yaml file, that manages zephyr repo and its dependencies.
Additionally west manifest may now control sof submodules.
Added submanifests directory with README.txt file so the
submanifests directory exists in version control - otherwise
west update command returns error. This is bug described in
https://github.com/zephyrproject-rtos/west/issues/594 .

Co-developed-by: Andrey Borisovich <andrey.borisovich@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-03 11:43:22 +01:00