Commit Graph

14 Commits

Author SHA1 Message Date
Daniel Leung 5f1e6900d9 zephyr: use k_smp_cpu_start/_resume for secondary core power up
This changes the secondary core power up routine to use the newly
introduced k_smp_cpu_start() and k_smp_cpu_resume(). This removes
the need to mirror part of the SMP start up code from Zephyr, and
no longer need to call into Zephyr private kernel code.

West update includes :

eefaeee061c8 kernel: smp: introduce k_smp_cpu_resume
042cb6ac4e00 soc: intel_adsp: enable DfTTS-based time stamping
             on ACE platforms
6a0b1da158a4 soc: intel_adsp: call framework callback function for restore
e7217925c93e ace: use a 'switch' statement in pm_state_set()
c99a604bbf2c ace: remove superfluous variable initialisation
a0ac2faf9bde intel_adsp: ace: enable power domain
4204ca9bcb3f ace: fix DSP panic during startup  (fixes c3a6274bf5e4)
d4b0273ab0c4 cmake: sparse.template: add COMMAND_ERROR_IS_FATAL
ca12fd13c6d3 xtensa: intel_adsp: fix a cache handling error
0ee1e28a2f5f xtensa: polish doxygen and add to missing doc
035c8d8ceb4b xtensa: remove sys_define_gpr_with_alias()
a64eec6aaeec xtensa: remove XTENSA_ERR_NORET

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
[guennadi.liakhovetski@linux.intel.com: update Zephyr hversion]
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-03-06 11:13:57 +02:00
Guennadi Liakhovetski 0e29dc690d multicore: don't enable timer interrupts on secondary cores
Keep timer interrupt handling on the primary core, this avoids
secondary cores failing to handle timer interrupts immediately after
power on.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-02-26 16:13:39 +00:00
Guennadi Liakhovetski 49abf3f54c multicore: add a timeout when enabling secondary cores
Replace a potentially infinite loop with one, using a retry counter
to avoid lock ups.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-02-26 12:21:39 +00:00
Jaroslaw Stelter 8cad5bea57 lib: alloc: Use aligned allocation for L3_HEAP usage.
L3_HEAP is used in library manager for library storage buffer allocation
and in D3 enter/exit flows to allocate IMR context storage buffer.
Both buffers should be aligned so use rballoc_align() routine to get
correctly aligned buffers.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2024-02-01 12:15:30 +02:00
Rander Wang b7858e8af1 zephyr: cavs: add secondary core context save support
Register pm_state_notifier to set ready_flag for secondary core when it
is powered up for second time after first fw boot. We can remove
CONFIG_ADSP_IMR_CONTEXT_SAVE check for cavs platform for this feature.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-11-09 11:17:43 +02:00
Rander Wang 9b08ce026d zephyr: cpu: use correct condition to init cpu
When converting #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE to if(IS_ENABLE(
CONFIG_ADSP_IMR_CONTEXT_SAVE), we should use if (!IS_ENABLE() ||

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-08-17 20:23:46 +03:00
Rander Wang 84befa2563 zephyr: cpu: init cpu if context save is not support
Fix multicore test issue on cavs platforms which don't support context
save now, so need to init cpu when the core boot up.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-08-16 13:43:38 +01:00
Flavio Ceolin 07455c572e zephyr: s/MP_NUM_CPUS/MP_MAX_NUM_CPUS/
Zephyr uses MP_MAX_NUM_CPUS internally to represent the
number of cores available and consequently to allocate
resources. It is even expected, and checked through assert,
that these two symbols have the same value. Use different
value can lead to an undesired behavior, so lets use
MP_MAX_NUM_CPUS.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-07-25 15:27:05 +01:00
Marcin Szkudlinski 4e8040c232 platform: ace: Add pm notifiers to support Zephyr's D3 transition
During PowerOff (D3) transition Zephyr Power Manager must have
a pointer in IMR to save the LP/HPSRAM memory before
powering off.

As zephyr has no access to IMR heap, the memory must
be allocated by SOF

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2023-06-28 15:32:16 +03:00
Tomasz Leman 93947f98a4 platform: ace: notifying about idle thread readiness
Informing the primary core that the Idle thread on secondary core is
ready. During the D3 exit flow thread is not initialize again, but
restored from previously saved context.

This patch includes also zephyr version update to aba3b12e31 (total 15
commits). Changes related to intel_adsp contain refactor and fixes for
ACE secondary cores power flows.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-05-11 19:08:28 +03:00
Tomasz Leman a048951286 zephyr: cpu: secondary core idle thread init
Idle thread should be initialize only when core it booting for the first
time. Doing this again would overwrite the kernel structs and the idle
thread stack.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-05-11 19:08:28 +03:00
Laurentiu Mihalcea f7d9e76f95 Remove unused <soc.h> header inclusions
This commit removes all occurrences of the soc.h header file
since this is not used. This also fixes build problem on i.MX93
caused by the fact that i.MX93 doesn't have a soc.h.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-04-24 11:40:53 +03:00
Jaska Uimonen e9cfb64f0d zephyr: cavs: use zephyr pm, clk and dma glue
Start using zephyr pm_runtime, clk and dma glue code in cavs25 native
drivers build. Move the files from ace/lib into zephyr/lib.

Also update west.yaml to related zephyr commit as power related
files have been moved to zephyr side.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2023-03-27 12:37:26 +03:00
Jaska Uimonen 1e21a5d2fc zephyr: lib: move cpu.c from lib-zephyr
Move zephyr cpu.c from "unnecessary" lib-zephyr to lib/zephyr.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2023-02-23 22:17:07 +00:00