Commit Graph

1298 Commits

Author SHA1 Message Date
Liam Girdwood 643652e796
Merge pull request #239 from tlauda/topic/idc_refactor_msg
idc: refactor IDC message template
2018-08-21 02:49:06 -07:00
Liam Girdwood cb5da1e7a9
Merge pull request #237 from tlauda/topic/work_queue_core_context
work: add work_queue to core_context
2018-08-21 01:46:05 -07:00
Tomasz Lauda e548d2ddf0 idc: refactor IDC message template
Refactors IDC message template to better distinguish
message type, header and extension.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-21 10:40:06 +02:00
Liam Girdwood 78f007daa9
Merge pull request #216 from singalsu/eq_iir_fix_ipc_proposal
EQ IIR: Update IPC to ALSA convention, fix channel bypass, and do cleanup
2018-08-20 08:21:44 -07:00
Tomasz Lauda 060c71e953 work: add work_queue to core_context
Implements work_queue per core by adding it to core_context.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-20 14:23:55 +02:00
Liam Girdwood 3f3055adfe
Merge pull request #236 from tlauda/topic/dw_dma_irq_refactor
dw-dma: refactor interrupt registration and unregistration
2018-08-20 03:25:44 -07:00
Seppo Ingalsuo 81d5bf3b3a EQ IIR: Update IPC to ALSA convention, fix channel bypass, and do cleanup
This patch updates binary IPC to similar style as done previously for FIR
equalizer. The blob size needs to be added as first word in the blob.

The internals of IIR coefficients format is exposed to uapi/eq.h level.
Also the blob parsing code is changed to use the structures instead of
hardcoded word offsets.

The EQ assign or switch to bypass (via -1) is fixed so there is no more
need to define a bypass EQ shape into the blob.

Finally C code style is updated to pass the commit checker scripts.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-20 13:13:13 +03:00
Tomasz Lauda b104a5dfdf dw-dma: refactor interrupt registration and unregistration
Changes flow of dw-dma interrupt registration and unregistration:
Now it is possible for slave cores to register for dw-dma handler.
Also registration happens before start and not on FW load
during probing. This way we are not wasting runtime heap memory
and also it will allow us to dynamically change execution core
for certain pipelines.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-20 12:08:31 +02:00
Liam Girdwood 2b8127640b
Merge pull request #227 from tlauda/topic/dcache_align
alloc: align memmap to cache line size
2018-08-20 02:47:58 -07:00
Tomasz Lauda c5ce41f2ab alloc: align memmap to cache line size
Aligns memmap related structs to cache line size.
This is getting us closer to have memory allocator
fully shared between cores.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-20 11:31:36 +02:00
Liam Girdwood 2b9be99f0d
Merge pull request #234 from RanderWang/apl_fw_ipc
apl: check host status before sending ipc msg in fw
2018-08-20 01:18:32 -07:00
Liam Girdwood b851d04e58
Merge pull request #235 from RanderWang/cnl_ipc_fw
cnl: check status of both host & fw before sending ipc msg in fw
2018-08-20 01:17:39 -07:00
Rander Wang 66a1bcf865 cnl: check status of both host & fw before sending ipc msg in fw
The busy bit of DIPCIDR register is cleared when host is ready,
and the done bit of DIPCIDA is cleared after fw confirms the
reply message from host. So fw should check these two conditions
before sending ipc msg to host

Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
2018-08-20 15:56:37 +08:00
Rander Wang 0db7e4877f apl: check host status before sending ipc msg in fw
The busy bit of DIPCI register is cleared when host is ready.
So fw could send ipc msgs to host when the value of busy bit
is zero

Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
2018-08-20 15:30:57 +08:00
Liam Girdwood dc6014f226 Merge remote-tracking branch 'gh/next' into gp20-alpha-drop-stable 2018-08-16 15:52:03 +01:00
Liam Girdwood 4e726e62bc
Merge pull request #226 from tlauda/topic/system_mem_master_core
alloc: system memory reserved for master core
2018-08-14 12:02:20 -07:00
Tomasz Lauda 56f52b96a3 memory: add cache_to_uncache and uncache_to_cache macros
Adds macros, which allows to retrieve cached/uncached version
of memory pointer.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-14 15:35:36 +02:00
Tomasz Lauda 7d38ed143e alloc: system memory reserved for master core
System memory should be reserved only for master core.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-14 15:24:06 +02:00
Liam Girdwood 2530814a0a
Merge pull request #218 from tlauda/topic/cpu_is_core_enabled
cpu: implement cpu_is_core_enabled function
2018-08-13 03:18:35 -07:00
Liam Girdwood bfc7e467f7
Merge pull request #214 from bkokoszx/ssp_slot_padding
drivers: apl-ssp: handle tdm mode in ssp
2018-08-13 03:17:24 -07:00
Bartosz Kokoszko 5562fa3d48 drivers: apl-ssp: handle tdm mode in ssp
I've added tdm support in ssp. Tdm mode has
padding at the end of each slot. Tdm mode is
enabled by tdm_per_slot_padding flag in
sof_ipc_dai_ssp_params struct.

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
2018-08-13 10:59:08 +02:00
Bartosz Kokoszko 9fe51a4b58 drivers: apl-ssp: code optimization for DSP_A/B
The only difference between DSP_A and DSP_B modes
is FSRT bit in sspsp register and start delay
set to 1 in DSP_A mode.

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
2018-08-13 10:52:06 +02:00
Tomasz Lauda 1dfac35461 work: add queue timesources per core
Adds additional work queue timesources for slave cores.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-13 08:01:38 +02:00
Liam Girdwood 86610e066d
Merge pull request #223 from plbossart/fix/ipc-header
uapi: ipc: align with kernel
2018-08-12 11:03:11 -07:00
Pierre-Louis Bossart 01100e50d3 uapi: ipc: align with kernel
It beats me why changes done one one side are not merged on the other.
We should really require all changes to the IPC files to be distinct
PRs so that they are easier to track.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2018-08-10 16:36:55 -05:00
Liam Girdwood 90d736cea3
Merge pull request #220 from tlauda/topic/idc_send_blocking
idc: allow to send blocking messages to cores
2018-08-10 05:26:04 -07:00
Liam Girdwood a1af7ff430
Merge pull request #219 from tlauda/topic/memory_cache_line_align
cavs: memory: align runtime heap buffers to cache lines
2018-08-10 04:17:10 -07:00
Liam Girdwood 2ed30b5b04
Merge pull request #213 from singalsu/eq_fir_blob_handling_fix_proposal
EQ FIR: Improve robustness with configuration blobs
2018-08-10 04:12:54 -07:00
Tomasz Lauda 332aac8f3b idc: allow to send blocking messages to cores
Adds functionality of sending blocking IDC messages
to other cores.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-10 12:25:37 +02:00
Tomasz Lauda 512de6044e cavs: memory: align runtime heap buffers to cache lines
Aligns every runtime heap buffer to cache line (64 bytes).
This way we won't have problem with processing tasks on slave cores
in the future.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-10 11:31:31 +02:00
Tomasz Lauda 5fca99ef58 cpu: implement cpu_is_core_enabled function
Adds cpu_is_core_enabled function to check for active cores.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2018-08-10 11:25:19 +02:00
Liam Girdwood 597194f3dd
Merge pull request #204 from RanderWang/dma_trace_apl
trace: refine dma trace algorithm for apl
2018-08-09 03:56:17 -07:00
Liam Girdwood 3fea877c35
Merge pull request #211 from xiulipan/shfix
scripts: version: fix version error when have no tags
2018-08-09 00:31:38 -07:00
Pan Xiuli 0e620cdb58 scripts: version: fix version error when have no tags
Tags may missing if we just clone the branch in some case such as in
travis CI.

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
2018-08-09 11:45:43 +08:00
Rander Wang bd84f96cb9 trace: refine reschedule time for dma trace
It is a simple fix for trace buffer overflowing at the boot
up time or debug mode FW. At boot up time, there are many trace
events for topology loading in very short time, the trace buffer
needs to be scheduled ASAP. 5us is the shortest time works on
every platforms.

Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
2018-08-09 11:15:02 +08:00
Seppo Ingalsuo 51233fe16d EQ FIR: Improve robustness with configuration blobs
This patch prevents an error if the EQ responses to channels mapping
table in the configuration blob contains less channels than current
number of channels in firmware. Without this check the lookup from blob
can go past the table. Reporting an error depended on successive blob
content to detect corrupt blob and was not guaranteed.

The situation is not changed to stop to error but instead extrapolate
the table by applying 1st channel EQ for additional channels. It e.g.
helps to duplicate mono effect EQ to all channels without need to make
blobs with mapping to match max. channels count of SOF. The used response
index for each channel can be seen from trace.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 16:45:56 +03:00
Liam Girdwood f4716b12b9
Merge pull request #203 from mwierzbix/unitTest-lib-bzero
test: lib/bzero: Added unit tests for lib/bzero.
2018-08-08 06:00:13 -07:00
Michal Jerzy Wierzbicki f393ae33d3 test: lib/bzero: Added unit tests for lib/bzero.
Signed-off-by: Michal Jerzy Wierzbicki <michalx.wierzbicki@linux.intel.com>
2018-08-08 13:53:34 +02:00
Liam Girdwood 1cdf8f12bb
Merge pull request #208 from plbossart/fix/trigger_stop_fail
dai: fix error handling when DMA is stuck
2018-08-08 02:19:59 -07:00
Liam Girdwood 20752b7a9b
Merge pull request #194 from singalsu/eq_fir_optimize_proposal
EQ FIR optimize proposal
2018-08-08 02:10:02 -07:00
Liam Girdwood 2b034e7581
Merge pull request #183 from dabekjakub/pipeline_test
New pipeline test
2018-08-08 02:08:45 -07:00
Seppo Ingalsuo 920dc98f95 EQ FIR: HiFiEP optimized version
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 11:12:55 +03:00
Seppo Ingalsuo 57f186193a EQ FIR: HiFi3 optimized version
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 11:12:55 +03:00
Seppo Ingalsuo 32e490229b EQ FIR: Updates to generic C filter core
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 11:12:44 +03:00
Seppo Ingalsuo 639b4a8cd3 EQ FIR: Makefile changes for HiFiEP and HiFi3 optimized equalizer
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 10:49:24 +03:00
Seppo Ingalsuo 6b936a37a1 EQ FIR: Changes to support Xtensa optimized versions and updated IPC
This patch add possibility to use two samples per call processed
filter core. The use of optimized version depends on FIR core header
files settings. Normally when compiled with xt-xcc the optimized filter
version will be used.

The set data and get data IPC is updated to use binary and enum control
commands.

A pass-trough copy function is added get working pipeline with
non-configured EQ.

The full-circular EQ copy function is needed since it is unnecessary.
Normal SOF components work with buffers

EQ mute is removed since SOF components do not usually support it except
volume.

The IPC is updated to match ALSA binary and enum controls style. The
previous approach was not practical for kernel driver side.

Code style is updated the pass the checks.

Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2018-08-08 10:49:15 +03:00
Pierre-Louis Bossart a2054ae60d dai: fix error handling when DMA is stuck
When the DMA is stuck, e.g. in slave mode when the external clock is
not active, the Linux kernel will trigger a stop after a
timeout. Since the DMA will never complete, the current code returns
an IPC error on stop (DMA completion fails) and will not reset DMA
channel status and reference counts.

Force the DMA and DAI to be stopped to solve the problem. We probably
need to look at all error handling since it's likely to be a recurring
issue.

Also simplify the Xrun code, no need for an extra return.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2018-08-07 16:18:55 -05:00
Liam Girdwood 31d8aa4c7a
Merge pull request #207 from xiulipan/travisciupdate
ci: travis: update to use docker hub image
2018-08-07 09:41:41 -07:00
Liam Girdwood 8ab4c61faa
Merge pull request #205 from xiulipan/dockerupdate
scripts: docker: update gcc cross compiler to 8.1
2018-08-07 09:40:14 -07:00
Liam Girdwood 7e5823d8b0
Merge pull request #199 from mwierzbix/rstrcmp_nullTerminatorCheck
lib: rstrcmp: null terminator check
2018-08-07 09:39:40 -07:00