icl, cml whl are sharing some toplogy files. Create platform specific files
including DSP configuration, SSP setting and DMIC to simplify platform
settings.
Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
DMIC01 is just useless for a user. After multiple rounds of
discussion, we agreed to remove numbers (which could be understood as
a mic position) or a frequency (which is misleading since it can be
updated to e.g. 96kHz by topology), so by default the DMIC interface
is called just that...
Conversely, we add a clear 16kHz qualifier for the low-frequency
path. While in theory the frequency can be changed with modifications
of the FIR filter, applications do need 16kHz support.
Also make sure we only use 'DMIC' for 'PCH-attached DMICs'. For
RT715-based solutions, the microphones can be analog, so use more
generic 'Microphones' description.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This patch mitigates the start transient in capture from rt715
codec. The start transient is DC pulse that can be attenuated
significantly with a high-pass filter. The pipeline macro
pipe-highpass-capture.m4 adds a 40 Hz second order IIR filter
into the beginning of pipeline. The volume control in this pipeline
is also set to a longer 400 ms ramp length (normally 250 ms) that
is sufficient to conceal PCM waveform issues before the IIR filter
settles to DC level.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Due to clock frequency limitation on CML, the bandwidth is not enough
when playback and capture are opened at the same time if we use 32 bps.
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reverts all previosly changed cAVS pipelines from 3 to 2 periods.
Now we have separate buffers for DMA, so there is no need to make
DAI buffers consist of 3 periods. DMA will take care of any internal
hardware requirements.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Switches all pipelines for cAVS platforms to timer scheduling.
This way we limit the number of interrupt levels processed
in the system. Timer, IPC and IDC are already on level 2 and
DMAs are on level 5.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP, DMIC and ALH DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Bard Liao