Reverts all previosly changed cAVS pipelines from 3 to 2 periods.
Now we have separate buffers for DMA, so there is no need to make
DAI buffers consist of 3 periods. DMA will take care of any internal
hardware requirements.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Switches all pipelines for cAVS platforms to timer scheduling.
This way we limit the number of interrupt levels processed
in the system. Timer, IPC and IDC are already on level 2 and
DMAs are on level 5.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Fixes SSP format and used pipeline macro in CML topologies.
Fixes: cfe81f5127 ("topology: cml: cnl: use 3 periods for SSP, DMIC and ALH DAIs")
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP, DMIC and ALH DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
With m/n divider support, we can now support 24 bit/ 48k
on max98357a.
Add check to only use update BCLK if m/n support is present.
Else fallback to older settings.
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Enable setting pcm min and max rate from top level m4 pipeline macro.
This way it is possible to configure the whole pipeline to correct
samplerate range in 1 file. Previously you needed to modify the pipeline
macros where the rate was hardcoded. As the frame count is calculated
from pcm/dai rate and scheduling time the frame count is obsolete.
Introduce pipeline rate parameter to help configuring components with
fixed output rate. We can't deduce this from pcm range since for example
src might accept bigger max rate than the following dai. Even though the
parameter is named "pipeline rate" it essentially means the "final"
output rate to which this pipeline is connected to (dai or other
pipeline). In capture pipelines it means the originating fixed dai rate.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
Fred Oh