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2 Commits

Author SHA1 Message Date
Tomasz Leman 5b8ba30694 ace: overlay: update clock frequency 
Changing max clock frequency for FPGA configuration.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
 2023-09-28 07:53:37 +02:00
Jaroslaw Stelter 02635875fb lnl: Lunarlake configuration 
Add initial LNL configuration.
Enable building for xt-clang.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
 2023-05-24 18:52:53 +03:00