Commit Graph

80 Commits

Author SHA1 Message Date
Kai Vehmanen 7d5c3238e3 west.yml: upgrade zephyr to e40859f7
Total of 1128 commits, including following related to
dma-dw/intel_adsp/sparse/dmic/xtensa:

e40859f78712 Revert "dma: dw: Do not program SAR/DAR and CTL_HI/LO when using HW LLI"
7a85983ebcf2 xtensa: remove ELF section address rewriting
b32b321f502a dma: dw: Poll to check for channel disable with timeout
6226f9e6e44f dma: dw: fix the return value check
08d9efb202cc dma: dw: Do not program SAR/DAR and CTL_HI/LO when using HW LLI
045c68673491 dma: dw: Add a debug utility function
bd705e68b048 soc: xtensa: esp32: increase shared memory region
9854c915ffdf intel_adsp: cpu init refactor
9d5c21d58003 dts: xtensa: nxp: remove unused include
68c1cafb411e intel_adsp: dts: ace: lower case 71C00 to fix DTC warning
a8c0123d3c54 intel_adsp: cmake: add_custom_command(.mod) to fix incremental build
b00c63e7640c footprint: ci: Remove audio SOF samples
1efaa94bc64b drivers: audio: dmic_nrfx_pdm: drop -pin support
8ef2cd20d90a Drivers: DAI: Intel: DMIC: Shorten unmute ramp time
eead89e7f22d soc: intel_adsp: cavstool.py: simplify asyncio.run() call
cdae0bb7596e boards: intel_adsp_ace15_mtpm uses xcc-clang toolchain for twister

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-03-22 15:48:52 +02:00
Guennadi Liakhovetski 9aa2c13356 build: upgrade to the current rimage upstream
Upgrade to the present rimage upstream version to fix tgl building
with Zephyr main branch head.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-03-21 22:14:11 +00:00
Keqiao Zhang 634c65fa47 west.yml: upgrade rimage to d32db50
Pull in following rimage changes:

d32db50 mtl: add Aria module to extended manifest
5bc2010 rimage: fix build error
35bc644 mtl: add eq-iir and fir support
6fad356 rimage: Removed hash context from image structure
6c7a151 hash: Remove old hash functions
d258ea2 manifest: pkcs1_5: Use new hash functions
2bd8be3 hash: New hash functions
93c5e8b misc_utils: Move byte_swap function to new misc_utils.c file
9ce1cc8 ext_manifest: Fix fw_ext_man_cavs_header version
a4ca53c toml_utils: Adding support for decimal numbers in hex parser
5ebbd65 rimage: use hex number
36c0c90 elf: Use the get_file_size function
98c7f7b manifest: Use the get_file_size function
6a64cb9 file_utils: Add a new get_file_size function
055ea7e file_utils: manifest: ext_manifest: Add new create_file_name function
fed69d4 toml_utils: adsp_config: Moved generic parser functions to toml_utils
0931d9c main: heap_adsp release fix
3aa199f config: mtl: set init_config for micsel
d48ad6b adsp_config: add dump for init_config
ffd0542 adsp_config: make the default value zero for init_config
cb9c880 config: tgl-cavs: add kpb, selector and kd support
bf23b5e config: mtl: set KDTEST module_type to 8

Signed-off-by: Keqiao Zhang <keqiao.zhang@intel.com>
2023-03-08 14:12:06 +02:00
Andrey Borisovich b2073f1f26 west.yml: upgrade Zephyr to e3ae110a05d
Includes:
- rename of xcc-clang compiler to xt-clang
- updates in C++ headers in zephyr/sys/util.h that require C++14
standard now.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-02-28 14:59:41 +00:00
Jaska Uimonen 5efc08d5aa dai: change to use new version of dai_config_get
Start using new version of dai_config_get where config struct is given
as pointer argument.

Update west.yaml to point to correct zephyr version for this change.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2023-02-21 15:45:17 +00:00
Kai Vehmanen a942f10731 west.yml: upgrade Zephyr to 0c0d73721ed
Includes patches to dai-zephyr.c to adapt to DMA interface
change for DW/HDDMA drivers.

Total of 1168 commits, including following related to
intel_adsp/sparse/dmic/xtensa:

8f5bcb2e76c3 intel_adsp: ace: fix linker script for xcc-clang compiler
18ce85c20130 tests: intel_adsp: ssp: fix dma data sizes
60a20471b561 intel_adsp: ace: enable interrupts for secondary core
6045eed2f361 intel_adsp: ace: enable core power gating
e1dbc2efef50 intel_adsp: ace: add core power off step
a99b073392fc intel_adsp: ace: d3 exit update
156c7cd21759 intel_adsp: bbzero/bmemcpy with picolibc fix
60196ca1126a cmake: sparse: deprecate old sparse support
91902c5fd4db cmake: add sparse support to the new SCA infrastructure
a684714d5c82 soc: intel_adsp: Correct HDA parameter docstrings
db495a5ebee3 xtensa: stop execution under simulator for double exception
8ff88346955b xtensa: sparse: fix address space mismatch
7965fd2b4a8a samples/boards/intel_adsp: Make sample work with twister
422250d3b183 mm: intel_adsp_mtl_tlb: suppress sparse address space warnings
618a478ded70 xtensa: fix sparse warning when converting to uncache pointer
8b391dc43841 drivers: audio: dmic_nrfx_pdm: Fix a race condition in the driver
8794de2934f7 intel_adsp: soc: ace: Add communication widget driver
a9b3d935500c intel_adsp: dai: Add support for ALH up to 16 nodes
837432506269 drivers: dai: intel: dmic: don't use assert for error handling

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-02-21 10:14:17 +00:00
Kai Vehmanen 00442c2310 west.yml: upgrade rimage to 3863e94fa5
Pull in following rimage changes:

3863e94fa5 Don't convert ROM addresses to cached aliases
1e0a85b44a config:tgl/tglh: Do not set cached/uncached address aliases
9b507ecc82 config: set cached and uncached aliases for affected platforms
def9d51d7d Fix regression - make default return code an error
d48ae7aada config: mtl: Set init_config for smart amp
b5d762290f config: tgl-cavs: set init_config for smart test
15ea48177a src: adsp_config: Use reserved bits for module init config
ec649f37d6 Convert all ELF addresses to cached for calculations

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-02-14 15:33:24 +00:00
Jaska Uimonen 4d735045a0 west.yml: upgrade rimage to 7bc3cfc
upgrade rimage to
7bc3cfc946

7bc3cfc config: mtl: add smart amp test module config
3da7739 config: correct module config load_type
bc7d49d config: align module_type with mtl for tgl and tgl-h
bdf48ee config: tgl-cavs: add fir and iir eq module config

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2023-02-07 14:46:53 +00:00
Adrian Warecki 1fbd4c6605 zephyr: ace: pm_runtime: Use new register name & update zephyr revision
DFDSPBRCP register have been renamed to DSPCS in Zephyrs commit
21f278c04bc258eb344ac5b2123b49d760b5b71d. This commit changes the
references from old to new name.

Changed zephyr revision to d9c4ec31fc49e7eef3c8c3b0d07827cc04e6efee

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-01-13 13:11:08 +02:00
Serhiy Katsyuba 05b903bc29 west.yml: Update Zephyr
Updates Zephyr to current top: e4fcb32451c587a3e4ba7f8bf3fc602b16f9652b.

This is to enable ALH multi-gateway feature. The required Zephyr commit
for Intel ADSP MTL is:
https://github.com/zephyrproject-rtos/zephyr/pull/53066

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-01-06 15:15:42 +00:00
Jaska Uimonen 39ff8cdbea west.yml: upgrade rimage to ba8534bb23
upgrade rimage to
ba8534bb23

ba8534bb23 Fix bitmap according to the IMR type
f3eef3cfb6 Fix IMR type parsing
bdba8259fe Add a command line option to set an Intel-specific PV bit
1c48208850 config: tgl-cavs: add smart amp test module config
082b6261c9 config: Add mt8188.toml

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2023-01-05 15:05:11 +02:00
Tomasz Leman 8368a6c9f4 west.yml: upgrade zephyr to 720787f75a
Zepych update: total of 73 commits.

Changes include adding power domains to DMA interfaces and allowing to
skip context save during d3.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-21 18:20:36 +02:00
Kai Vehmanen dba643cf2b west.yml: upgrade Zephyr to c5b270e7b003
Total of 440 commits, including following related to
intel_adsp/sparse/dmic/xtensa:

603cc2704579 dma: Add max block count attribute
2c162449eb4c xtensa: linker: Fix #52539 by updating the linker scripts
2dd4cbc75592 dts: xtensa: intel: update cavs25_tgph to match cavs25

Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-12-15 12:36:03 +02:00
Tomasz Leman 192fda25a8 west.yml: upgrade zephyr to 56284d7017
Zepych update: total of 40 commits.

Update needed before enabling power domains.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-12-09 15:50:22 +00:00
Ievgen Ganakov 6db472f429 west.yml: update rimage to 65f345a52
Update rimage to
65f345a52e06a084192124364c563d8133d834c2v

65f345a rimage: add src support
fe5b959 rimage: correct module type
f51ff46 rimage: remove incorrect module order check
6623073 config: mtl: add kpb module
85a2d1e config: mtl: add kd module

Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
2022-11-30 11:58:46 +00:00
Marcin Szkudlinski e4f7e518e8 Update zephyr revision
Updated zephyr to the latest version with
the necessary patches
a requried kconfig option is added because of
https://github.com/zephyrproject-rtos/zephyr/pull/51738

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2022-11-30 09:56:35 +01:00
Adrian Warecki 1f9da7ea0f Update zephyr revision
Updated zephyr to the latest version with
the necessary patches

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2022-11-28 16:55:55 +02:00
Marc Herbert 19d2fbb625 west.yml: remove self.path: sof
The intent was to stop people from cloning the sof manifest git repo
under a different name than "sof". It did not work, I had to help
multiple people who did it anyway.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-11-09 14:15:07 +00:00
Kai Vehmanen a0d9a4e4ac west.yml: upgrade Zephyr to 2e66fac6d3ff
Total of 946 commits, including following related to
intel_adsp/sparse/dmic/xtensa:

728506df6f45 soc: intel_adsp/ace: wait for lpsram power up
7e0c1a81cb54 soc: intel_adsp/ace: remove z_delay from hpsram init
e3e24b266d2d soc: xtensa: intel_adsp: ace: Fix build when CONFIG_MP_NUM_CPUS=1
dbc366918d8f tests: Enable qemu_xtensa logging tests
2dc9257ae1ae drivers: dmic: remove invalid assert on dmic->created
a574957c7457 soc: xtensa: intel_adsp: ace: set number of cpus at boot
7ffc6c31b555 samples/boards: Add intel_adsp/code_relocation sample
e98a748ad24e soc/xtensa/intel_adsp/cavs: Support for code relocation
06990e69d676 soc/xtensa/intel_adsp/cavs: Expose linker script on include
8ac6f74a7de5 arch/xtensa: Enable code relocation
fb26f18ae1c3 soc/xtensa/sample_controller: Expose linker script on include
d7f46136e013 soc/xtensa: Use standard __data_start/__data_end markers
f5dc229bc5df drivers: wifi: esp32: add softap config
dd1c88d54862 dts: xtensa: intel: fix alh base addr for cavs25
1f6d6deaef44 sparse: fix sparse warnings found in sof compilation
af5fb91a6c1f soc: intel_adsp: ipc: Do not send message until previous one is acked
0a7c25e649d1 drivers: timer: intel_adsp: Update driver to use dts Kconfig symbol
b953ff1418d2 drivers: dmic: enable dmic mono configuration
bedc2e7ab436 drivers: dmic: remove soft_reset from dmic init flow
39c2007b04ec drivers: dmic: update dmic flow initialization
ba0617417a1d tests: intel_adsp: smoke: Convert CONFIG_MP_NUM_CPUS handling
f8fba49a4102 soc: xtensa: intel_adsp: Convert CONFIG_MP_NUM_CPUS handling
0ce0f43b36bd soc: xtensa: esp32: Convert CONFIG_MP_NUM_CPUS handling
9387d8689b32 soc: xtensa: esp32: Add CONFIG_SMP protection
ad05e795986f intel_adsp: mem_window: fix definition of memory windows
f09a3a1bd675 linker: intel_adsp: discard GNU-stack notes
5760fcc8ab42 soc: xtensa: esp32_net:
b09973c460e3 soc: intel_adsp/common: remove reference to hp_sram_pm_banks
a2cb4a7ce3b9 soc: intel_adsp/ace: always inline funcs to get memory bank cnt
3ffe2654268a soc: intel_adsp/common: only memcpy segment if needed
195db14400f2 soc: intel_adsp/ace: zero out memory at ram init

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-11-08 17:58:09 +02:00
Kwasowiec, Fabiola cd2c44389f west.yml: upgrade rimage to 3ee717eebc
upgrade rimage to
3ee717eebc

3ee717eebc probe: mtl.toml invaliv probe type
1f4a36e21f mux: fix module type
dcfd11bc4d mux: add mux cfg to list of modules
d957e0368b rimage: make ace15 signing to support openssl3
a1b6e6db33 manifest: add fw_ver_micro to manifest
fb28357912 config: mtl: add probe module

Signed-off-by: Kwasowiec, Fabiola <fabiola.kwasowiec@intel.com>
2022-10-20 11:09:53 +02:00
Marc Herbert 8fd351ea9a west.yml: add warning to keep git submodules in sync
Trying avoid out-of-sync situations like commit a3b3c525d1 ("west:
update to newer rimage baseline").

Also explain why sof cannot be cloned as "sof2"

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-10-13 10:47:49 -07:00
Kai Vehmanen 5702939836 west.yml: upgrade Zephyr to ed661a6c6909
Upgrade Zephyr from 0956647aaf6bd2b1e840adcc86db503f274d84a9 to
ed661a6c6909b338035b026cfc101ddda65ab8eb (1020 commits, including
441 since v3.2.0 tag).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-10-13 14:55:26 +03:00
Peter Ujfalusi a3b3c525d1 west: update to newer rimage baseline
tgl-h zephyr build is broken due to outdated rimage revision.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2022-09-27 17:19:15 +01:00
Marc Herbert 3d69a7f69e .github: extend yamllint line-length to 100
Also run on west.yml

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-09-26 12:33:56 +01:00
Kai Vehmanen d525235e0e west.yml: upgrade Zephyr to 3.2.0-rc1 level
Update Zephyr to 0956647aaf6bd2b1e840adcc86db503f274d84a9 (3.2.0-rc1
plus a few fixes merged to upstreamed after the tag).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-09-15 13:54:24 +01:00
Kai Vehmanen b965236529 west: update to newer Zephyr baseline
Update zephyr to commit dcda3eab8df7 ("tests: net: socket: tcp: move to
new ztest API").

Needed to bring in support for Intel mtrace logging backend.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-31 10:33:46 +01:00
Kai Vehmanen 5fb1d45562 west: update to newer Zephyr baseline
Update zephyr to commit 8e55e59c5917 ('arch: introduce config DCLS').

Fixes build errors due to missing core-isa.h with tgl Intel target with
gcc build chain.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-05 15:52:45 +01:00
Marc Herbert dfaf9b8f28 west.yml: clarify warning about ignored zephyr/west.yml changes
Fixes commit 2c9772d5ad ("Add west.yml configuring zephyr
dependencies from sof")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-08-04 09:46:22 +01:00
Andrey Borisovich 70406a0db0 scripts: added versioning to xtensa-build-zephyr.py and west manifest
Added versioning to scripts/xtensa-build-zephyr.py to get version
information when incompatible changes are done to the script.
Added yml schema version number to west.yml manifest.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-08-03 11:43:22 +01:00
Krzysztof Frydryk 2c9772d5ad Add west.yml configuring zephyr dependencies from sof
Added west.yaml file, that manages zephyr repo and its dependencies.
Additionally west manifest may now control sof submodules.
Added submanifests directory with README.txt file so the
submanifests directory exists in version control - otherwise
west update command returns error. This is bug described in
https://github.com/zephyrproject-rtos/west/issues/594 .

Co-developed-by: Andrey Borisovich <andrey.borisovich@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-03 11:43:22 +01:00