Commit Graph

5 Commits

Author SHA1 Message Date
Pierre-Louis Bossart b00869e204 topology: fix DMIC device names
DMIC01 is just useless for a user. After multiple rounds of
discussion, we agreed to remove numbers (which could be understood as
a mic position) or a frequency (which is misleading since it can be
updated to e.g. 96kHz by topology), so by default the DMIC interface
is called just that...

Conversely, we add a clear 16kHz qualifier for the low-frequency
path. While in theory the frequency can be changed with modifications
of the FIR filter, applications do need 16kHz support.

Also make sure we only use 'DMIC' for 'PCH-attached DMICs'. For
RT715-based solutions, the microphones can be analog, so use more
generic 'Microphones' description.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2020-01-21 16:21:26 +00:00
Tomasz Lauda 79efa9391c topology: revert all cAVS pipelines to 2 periods
Reverts all previosly changed cAVS pipelines from 3 to 2 periods.
Now we have separate buffers for DMA, so there is no need to make
DAI buffers consist of 3 periods. DMA will take care of any internal
hardware requirements.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-24 10:17:03 +02:00
Tomasz Lauda 6fa4e4c8ae topology: cavs: switch all pipelines to timer scheduling
Switches all pipelines for cAVS platforms to timer scheduling.
This way we limit the number of interrupt levels processed
in the system. Timer, IPC and IDC are already on level 2 and
DMAs are on level 5.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-16 14:16:18 +02:00
Tomasz Lauda 5a3546595b topology: tgl: use 3 periods for SSP and DMIC DAIs
Changes number of SSP and DMIC DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-11 14:17:29 +02:00
Pan Xiuli 3f4c3c8286 topology: add tigerlake nocodec support
Enable SSP0/1/2 and DMIC01 nocodec topology for tigerlake.

Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com>
2019-08-28 12:20:20 +02:00