Clean up an incorrect TODO comment in the power management runtime
policy.
The removed comment suggested the need for substates to handle cases where
power gating (PG) is enabled and clock gating (CG) is disabled. However,
this is not accurate because:
- Enabling PG when CG is not allowed is not feasible; entering PG could
inadvertently gate the clock even if CG prevent is active.
- Substates are no longer required as clock gating is now always enabled.
This change clarifies the power management behavior and removes confusion
around the handling of power and clock gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The DSP cannot enter the power gating state if it has not yet received
an ack from host after sending an ipc message.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Start using zephyr pm_runtime, clk and dma glue code in cavs25 native
drivers build. Move the files from ace/lib into zephyr/lib.
Also update west.yaml to related zephyr commit as power related
files have been moved to zephyr side.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
Tomasz Leman