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topology: schedule two KWD pipelines on 5 ms period 

This patch changes the KWD pipelines perriod from 20 ms
to 5 ms to improve performance.

Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This commit is contained in:
Marcin Rajwa 2020-07-14 13:41:49 +02:00 committed by Liam Girdwood
parent 665bda9c8a
commit fec09e0b87
2 changed files with 2 additions and 2 deletions
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2
tools/topology/sof-cml-rt5682-kwd.m4
View File

@ -19,7 +19,7 @@ include(`abi.h')
# Include Platform specific DSP configuration
include(`platform/intel/'PLATFORM`.m4')
define(KWD_PIPE_SCH_DEADLINE_US, 20000)
define(KWD_PIPE_SCH_DEADLINE_US, 5000)
DEBUG_START

2
tools/topology/sof-tgl-max98357a-rt5682.m4
View File

@ -84,7 +84,7 @@ define(DMIC_PIPELINE_16k_ID, `11')
define(DMIC_PIPELINE_KWD_ID, `12')
define(DMIC_DAI_LINK_16k_ID, `2')
# define pcm, pipeline and dai id
define(KWD_PIPE_SCH_DEADLINE_US, 20000)
define(KWD_PIPE_SCH_DEADLINE_US, 5000)
# include the generic dmic with kwd
include(`platform/intel/intel-generic-dmic-kwd.m4')