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intel: drivers: dmic refactor - move DMIC_HW_IOCLK to Kconfig 

Moved hardcoded cycles values for DMIC IO from dmic.h header
to per-platform configuration file (defconfig files for
non-Zephyr builds and app/boards for Zephyr builds).
Added new entry to intel drivers Kconfig - CONFIG_DMIC_HW_IOCLK.
Modification of this clock value may be used for testing purposes
like building firmware for FPGA or simulator.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This commit is contained in:
Andrey Borisovich 2022-08-16 02:35:22 +02:00 committed by Liam Girdwood
parent e1d2b8d1a3
commit f8e111eb27
20 changed files with 31 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
app/boards/intel_adsp_cavs15.conf
View File

@ -1,5 +1,6 @@
CONFIG_APOLLOLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=19200000
CONFIG_INTEL_SSP=y
CONFIG_LP_MEMORY_BANKS=2
CONFIG_HP_MEMORY_BANKS=8

1
app/boards/intel_adsp_cavs18.conf
View File

@ -1,5 +1,6 @@
CONFIG_CANNONLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=24000000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
app/boards/intel_adsp_cavs20.conf
View File

@ -1,5 +1,6 @@
CONFIG_ICELAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
app/boards/intel_adsp_cavs20_jsl.conf
View File

@ -1,5 +1,6 @@
CONFIG_ICELAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=16

1
app/boards/intel_adsp_cavs25.conf
View File

@ -1,5 +1,6 @@
CONFIG_TIGERLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
app/boards/intel_adsp_cavs25_tgph.conf
View File

@ -1,5 +1,6 @@
CONFIG_TIGERLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
src/arch/xtensa/configs/apollolake_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_APOLLOLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=19200000
CONFIG_INTEL_SSP=y
CONFIG_CORE_COUNT=1
CONFIG_LP_MEMORY_BANKS=2

1
src/arch/xtensa/configs/cannonlake_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_CANNONLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=24000000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
src/arch/xtensa/configs/cannonlake_gcc_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_CANNONLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=24000000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_CAVS_LPS=y

1
src/arch/xtensa/configs/icelake_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ICELAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

1
src/arch/xtensa/configs/jasperlake_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ICELAKE=y
CONFIG_RIMAGE_SIGNING_SCHEMA="jsl"
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_CORE_COUNT=2
CONFIG_LP_MEMORY_BANKS=1

1
src/arch/xtensa/configs/suecreek_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_SUECREEK=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=19200000
CONFIG_INTEL_SSP=y
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=47

1
src/arch/xtensa/configs/suecreek_gcc_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_SUECREEK=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=19200000
CONFIG_INTEL_SSP=y
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=47

1
src/arch/xtensa/configs/tgph_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_TIGERLAKE=y
CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h"
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_CORE_COUNT=2

1
src/arch/xtensa/configs/tgplp_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_TIGERLAKE=y
CONFIG_INTEL_DMIC=y
CONFIG_DMIC_HW_IOCLK=38400000
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1

7
src/drivers/intel/Kconfig
View File

@ -52,6 +52,13 @@ config INTEL_DMIC
if INTEL_DMIC
config DMIC_HW_IOCLK
int "Set DMIC hw IO clock"
default 0
help
Hardware specific DMIC IO clock speed defined by each platform.
May be overridden from hardware values for simulation purposes.
choice
prompt "Driver operation mode"
default INTEL_DMIC_TPLG_PARAMS

2
src/drivers/intel/cavs/timestamp.c
View File

@ -102,7 +102,7 @@ int timestamp_dmic_config(struct dai *dai, struct timestamp_cfg *cfg)
return -EINVAL;
}
cfg->walclk_rate = DMIC_HW_IOCLK;
cfg->walclk_rate = CONFIG_DMIC_HW_IOCLK;
return 0;
}

14
src/drivers/intel/dmic/dmic_computed.c
View File

@ -67,7 +67,7 @@ static void find_modes(struct dai *dai,
/* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
if (dmic->global->prm[di].pdmclk_max < DMIC_HW_PDM_CLK_MIN ||
dmic->global->prm[di].pdmclk_max > DMIC_HW_IOCLK / 2) {
dmic->global->prm[di].pdmclk_max > CONFIG_DMIC_HW_IOCLK / 2) {
dai_err(dai, "find_modes(): pdm clock max not in range");
return;
}
@ -94,9 +94,9 @@ static void find_modes(struct dai *dai,
}
/* Min and max clock dividers */
clkdiv_min = ceil_divide(DMIC_HW_IOCLK, dmic->global->prm[di].pdmclk_max);
clkdiv_min = ceil_divide(CONFIG_DMIC_HW_IOCLK, dmic->global->prm[di].pdmclk_max);
clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN);
clkdiv_max = DMIC_HW_IOCLK / dmic->global->prm[di].pdmclk_min;
clkdiv_max = CONFIG_DMIC_HW_IOCLK / dmic->global->prm[di].pdmclk_min;
/* Loop possible clock dividers and check based on resulting
* oversampling ratio that CIC and FIR decimation ratios are
@ -112,7 +112,7 @@ static void find_modes(struct dai *dai,
du_max = 100 - du_min;
/* Calculate PDM clock rate and oversampling ratio. */
pdmclk = DMIC_HW_IOCLK / clkdiv;
pdmclk = CONFIG_DMIC_HW_IOCLK / clkdiv;
osr = pdmclk / fs;
/* Check that OSR constraints is met and clock duty cycle does
@ -140,7 +140,7 @@ static void find_modes(struct dai *dai,
mcic = osr / mfir;
ioclk_test = fs * mfir * mcic * clkdiv;
if (ioclk_test == DMIC_HW_IOCLK &&
if (ioclk_test == CONFIG_DMIC_HW_IOCLK &&
mcic >= DMIC_HW_CIC_DECIM_MIN &&
mcic <= DMIC_HW_CIC_DECIM_MAX &&
i < DMIC_MAX_MODES) {
@ -237,14 +237,14 @@ static struct pdm_decim *get_fir(struct dai *dai,
if (mfir <= 0)
return fir;
cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
cic_fs = CONFIG_DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
fs = cic_fs / mfir;
/* FIR max. length depends on available cycles and coef RAM
* length. Exceeding this length sets HW overrun status and
* overwrite of other register.
*/
fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX,
DMIC_HW_IOCLK / fs / 2 -
CONFIG_DMIC_HW_IOCLK / fs / 2 -
DMIC_FIR_PIPELINE_OVERHEAD);
i = 0;

2
src/drivers/intel/dmic/dmic_nhlt.c
View File

@ -567,7 +567,7 @@ int dmic_set_config_nhlt(struct dai *dai, void *spec_config)
return -EINVAL;
}
dmic->dai_rate = DMIC_HW_IOCLK / rate_div;
dmic->dai_rate = CONFIG_DMIC_HW_IOCLK / rate_div;
dai_info(dai, "dmic_set_config_nhlt(): rate = %d, channels = %d, format = %d",
dmic->dai_rate, dmic->dai_channels, dmic->dai_format);
return 0;

4
src/include/sof/drivers/dmic.h
View File

@ -38,28 +38,24 @@
#if CONFIG_APOLLOLAKE
#define DMIC_HW_VERSION 1
#define DMIC_HW_CONTROLLERS 2
#define DMIC_HW_IOCLK 19200000
#define DMIC_HW_FIFOS 2
#endif
#if CONFIG_CANNONLAKE
#define DMIC_HW_VERSION 1
#define DMIC_HW_CONTROLLERS 2
#define DMIC_HW_IOCLK 24000000
#define DMIC_HW_FIFOS 2
#endif
#if CONFIG_SUECREEK
#define DMIC_HW_VERSION 2
#define DMIC_HW_CONTROLLERS 4
#define DMIC_HW_IOCLK 19200000
#define DMIC_HW_FIFOS 2
#endif
#if CONFIG_ICELAKE || CONFIG_TIGERLAKE
#define DMIC_HW_VERSION 1
#define DMIC_HW_CONTROLLERS 2
#define DMIC_HW_IOCLK 38400000
#define DMIC_HW_FIFOS 2
#endif