OrgACRN
/
sof
mirror of https://github.com/thesofproject/sof.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

drivers: imx: edma: Introduce support for i.MX93's EDMA2 

Just like IMX8ULP i.MX93's EDMA2 uses a channel multiplexer
to assign a peripheral to a channel. To make the driver work
it's required to write the peripheral's line number to the
CH_MUX register.

This commit also introduces all macros necessary for EDMA2.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2023-04-10 12:21:23 +03:00 committed by Daniel Baluta
parent a706f40433
commit f783401e24
2 changed files with 29 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/drivers/imx/edma.c
View File

@ -285,7 +285,7 @@ static int edma_setup_tcd(struct dma_chan_data *channel, int16_t soff,
int dest_width, uint32_t burst_elems)
{
int rc;
#ifdef CONFIG_IMX8ULP
#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
struct dai_data *dd = channel->dev_data;
int direction, handshake, dmamux_cfg;
#endif
@ -335,7 +335,7 @@ static int edma_setup_tcd(struct dma_chan_data *channel, int16_t soff,
if (rc < 0)
return rc;
#ifdef CONFIG_IMX8ULP
#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
/* Do not write EDMA_CH_MUX register when it has value,
* otherwise the register will be cleared.
*/

27
src/include/sof/drivers/edma.h
View File

@ -98,6 +98,33 @@
#define EDMA0_SAI_CHAN_RX_IRQ 349
#define EDMA0_SAI_CHAN_TX_IRQ 349
#ifdef CONFIG_IMX93_A55
/* encase all of these macros in an
* ifdef block to avoid possible future
* naming clashes and pointlessly adding
* macros for all other platforms.
*/
#define EDMA2_SAI3_CHAN_RX 1
#define EDMA2_SAI3_CHAN_TX 0
/* EDMA2 (aka EDMA4 in the TRM) supports
* up to 64 channels.
*/
#define EDMA2_CHAN_MAX 64
/* need to add SPI_BASE to the INTID as
* the values from the TRM are all SPIs.
*/
#define EDMA2_SAI3_CHAN_RX_IRQ (128 + 32)
#define EDMA2_SAI3_CHAN_TX_IRQ (128 + 32)
/* SAI3 is connected to EDMA2 through
* lines 60 (TX) and 61 (RX).
*/
#define EDMA2_SAI3_TX_MUX 60
#define EDMA2_SAI3_RX_MUX 61
#endif /* CONFIG_IMX93_A55 */
/* EDMA doesn't bound channels to IPs, we make use of the first two channels for now */
#define IMX8ULP_EDMA2_CHAN0 0
#define IMX8ULP_EDMA2_CHAN1 1