OrgACRN
/
sof
mirror of https://github.com/thesofproject/sof.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

platform: mt8195: suspend switch clock back to 26M 

When DSP enter suspend:
1.Define CLK_SUSPEND_CPU_HZ 26M for DSP suspend frequency and turn
  off adsp pll clock to avoid unexpected behavior after resume.
2.Increase wait for interrupt level to 15 to avoid unexpected interrupts.
3.Remove XT_WAITI_DELAY for LX7.

Signed-off-by: YC Hung <yc.hung@mediatek.com>
This commit is contained in:
YC Hung 2022-02-25 10:47:45 +08:00 committed by Liam Girdwood
parent 8f78c7ecd6
commit f551fdb9fb
3 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/drivers/mediatek/mt8195/ipc.c
View File

@ -84,8 +84,10 @@ enum task_state ipc_platform_do_cmd(struct ipc *ipc)
void ipc_platform_complete_cmd(struct ipc *ipc)
{
trigger_irq_to_host_rsp();
while (ipc->pm_prepare_D3)
wait_for_interrupt(0);
while (ipc->pm_prepare_D3) {
clock_set_freq(CLK_CPU(cpu_get_id()), CLK_SUSPEND_CPU_HZ);
asm volatile("waiti 15");
}
}
int ipc_platform_send_msg(const struct ipc_msg *msg)

1
src/platform/Kconfig
View File

@ -267,7 +267,6 @@ config MT8195
select XT_INTERRUPT_LEVEL_3
select DUMMY_DMA
select HOST_PTABLE
select XT_WAITI_DELAY
select MEDIATEK
select XTENSA_EXCLUSIVE
select SCHEDULE_DMA_MULTI_CHANNEL

1
src/platform/mt8195/include/platform/lib/clk.h
View File

@ -19,6 +19,7 @@ struct sof;
#define CLK_DEFAULT_CPU_HZ 720000000
#define CLK_MAX_CPU_HZ 720000000
#define CLK_SUSPEND_CPU_HZ 26000000
#define NUM_CLOCKS 1