mirror of https://github.com/thesofproject/sof.git
dw-dma: add support for interrupt per channel
On Apollolake, the interrupt number for different channels of the same controller are different, here add implementation of it: register interrupt handler for each channel, and don't need check channel in its specific handler anymore. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
This commit is contained in:
Keyon Jie
Liam Girdwood
parent
0505823b96
commit
eea19e6578
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@ -821,6 +821,194 @@ static inline void dw_dma_chan_reload_next(struct dma *dma, int channel,
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dw_write(dma, DW_DMA_CHAN_EN, CHAN_ENABLE(channel));
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}
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static void dw_dma_setup(struct dma *dma)
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{
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struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data;
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int i;
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/* we cannot config DMAC if DMAC has been already enabled by host */
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if (dw_read(dma, DW_DMA_CFG) != 0)
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dw_write(dma, DW_DMA_CFG, 0x0);
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/* now check that it's 0 */
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for (i = DW_DMA_CFG_TRIES; i > 0; i--) {
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if (dw_read(dma, DW_DMA_CFG) == 0)
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goto found;
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}
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trace_dma_error("eDs");
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return;
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found:
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for (i = 0; i < DW_MAX_CHAN; i++)
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dw_read(dma, DW_DMA_CHAN_EN);
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#ifdef HAVE_HDDA
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/* enable HDDA before DMAC */
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shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH);
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#endif
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/* enable the DMA controller */
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dw_write(dma, DW_DMA_CFG, 1);
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/* mask all interrupts for all 8 channels */
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dw_write(dma, DW_MASK_TFR, INT_MASK_ALL);
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dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL);
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dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL);
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dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL);
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dw_write(dma, DW_MASK_ERR, INT_MASK_ALL);
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#ifdef DW_FIFO_PARTITION
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/* TODO: we cannot config DMA FIFOs if DMAC has been already */
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/* allocate FIFO partitions, 128 bytes for each ch */
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dw_write(dma, DW_FIFO_PART1_LO, 0x100080);
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dw_write(dma, DW_FIFO_PART1_HI, 0x100080);
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dw_write(dma, DW_FIFO_PART0_HI, 0x100080);
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dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26));
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dw_write(dma, DW_FIFO_PART0_LO, 0x100080);
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#endif
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/* set channel priorities */
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for (i = 0; i < DW_MAX_CHAN; i++) {
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#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL ||\
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defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
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dw_write(dma, DW_CTRL_HIGH(i),
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DW_CTLH_CLASS(dp->chan[i].class));
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#elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL
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dw_write(dma, DW_CFG_LOW(i),
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DW_CFG_CLASS(dp->chan[i].class));
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#endif
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}
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}
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#ifdef CONFIG_APOLLOLAKE
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/* external layer 2 interrupt for dmac */
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static void dw_dma_irq_handler(void *data)
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{
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struct dma_int *dma_int = (struct dma_int *)data;
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struct dma *dma = dma_int->dma;
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struct dma_pdata *p = dma_get_drvdata(dma);
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struct dma_sg_elem next;
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uint32_t status_tfr = 0, status_block = 0, status_err = 0, status_intr;
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uint32_t mask;
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int i = dma_int->channel;
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status_intr = dw_read(dma, DW_INTR_STATUS);
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if (!status_intr)
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trace_dma_error("eDI");
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trace_dma("irq");
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trace_value(status_intr);
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/* get the source of our IRQ. */
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status_block = dw_read(dma, DW_STATUS_BLOCK);
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status_tfr = dw_read(dma, DW_STATUS_TFR);
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/* TODO: handle errors, just clear them atm */
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status_err = dw_read(dma, DW_STATUS_ERR);
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if (status_err) {
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trace_dma_error("eDi");
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dw_write(dma, DW_CLEAR_ERR, status_err & i);
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}
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/* clear interrupts for channel*/
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dw_write(dma, DW_CLEAR_BLOCK, status_block);
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dw_write(dma, DW_CLEAR_TFR, status_tfr);
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/* skip if channel is not running */
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if (p->chan[i].status != COMP_STATE_ACTIVE) {
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trace_dma_error("eDs");
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return;
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}
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mask = 0x1 << i;
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#if DW_USE_HW_LLI
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/* end of a LLI block */
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if (status_block & mask &&
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p->chan[i].cb_type & DMA_IRQ_TYPE_BLOCK) {
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next.src = DMA_RELOAD_LLI;
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next.dest = DMA_RELOAD_LLI;
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/* will reload lli by default */
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next.size = DMA_RELOAD_LLI;
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p->chan[i].cb(p->chan[i].cb_data,
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DMA_IRQ_TYPE_BLOCK, &next);
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}
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#endif
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/* end of a transfer */
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if ((status_tfr & mask) &&
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(p->chan[i].cb_type & DMA_IRQ_TYPE_LLIST)) {
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trace_value(status_tfr);
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next.src = DMA_RELOAD_LLI;
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next.dest = DMA_RELOAD_LLI;
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next.size = DMA_RELOAD_LLI; /* will reload lli by default */
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if (p->chan[i].cb)
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p->chan[i].cb(p->chan[i].cb_data,
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DMA_IRQ_TYPE_LLIST, &next);
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/* check for reload channel:
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* next.size is DMA_RELOAD_END, stop this dma copy;
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* next.size > 0 but not DMA_RELOAD_LLI, use next
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* element for next copy;
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* if we are waiting for pause, pause it;
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* otherwise, reload lli
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*/
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switch (next.size) {
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case DMA_RELOAD_END:
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p->chan[i].status = COMP_STATE_PREPARE;
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break;
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case DMA_RELOAD_LLI:
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/* reload lli, but let's check if it is paused */
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if (p->chan[i].status != COMP_STATE_PAUSED)
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dw_dma_chan_reload_lli(dma, i);
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break;
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default:
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dw_dma_chan_reload_next(dma, i, &next);
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break;
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}
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}
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}
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static int dw_dma_probe(struct dma *dma)
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{
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struct dma_int *dma_int[DW_MAX_CHAN];
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struct dma_pdata *dw_pdata;
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int i;
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/* allocate private data */
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dw_pdata = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(*dw_pdata));
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dma_set_drvdata(dma, dw_pdata);
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spinlock_init(&dma->lock);
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dw_dma_setup(dma);
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/* init work */
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for (i = 0; i < dma->plat_data.channels; i++) {
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dw_pdata->chan[i].dma = dma;
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dw_pdata->chan[i].channel = i;
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dw_pdata->chan[i].status = COMP_STATE_INIT;
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dma_int[i] = rzalloc(RZONE_SYS, RFLAGS_NONE,
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sizeof(struct dma_int));
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dma_int[i]->dma = dma;
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dma_int[i]->channel = i;
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dma_int[i]->irq = dma->plat_data.irq +
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(i << REEF_IRQ_BIT_SHIFT);
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/* register our IRQ handler */
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interrupt_register(dma_int[i]->irq,
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dw_dma_irq_handler,
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dma_int[i]);
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interrupt_enable(dma_int[i]->irq);
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}
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return 0;
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}
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#else
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/* this will probably be called at the end of every period copied */
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static void dw_dma_irq_handler(void *data)
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{
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@ -915,64 +1103,6 @@ static void dw_dma_irq_handler(void *data)
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}
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}
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static void dw_dma_setup(struct dma *dma)
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{
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struct dw_drv_plat_data *dp = dma->plat_data.drv_plat_data;
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int i;
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/* we cannot config DMAC if DMAC has been already enabled by host */
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if (dw_read(dma, DW_DMA_CFG) != 0)
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dw_write(dma, DW_DMA_CFG, 0x0);
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/* now check that it's 0 */
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for (i = DW_DMA_CFG_TRIES; i > 0; i--) {
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if (dw_read(dma, DW_DMA_CFG) == 0)
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goto found;
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}
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trace_dma_error("eDs");
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return;
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found:
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for (i = 0; i < DW_MAX_CHAN; i++)
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dw_read(dma, DW_DMA_CHAN_EN);
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#ifdef HAVE_HDDA
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/* enable HDDA before DMAC */
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shim_write(SHIM_HMDC, SHIM_HMDC_HDDA_ALLCH);
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#endif
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/* enable the DMA controller */
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dw_write(dma, DW_DMA_CFG, 1);
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/* mask all interrupts for all 8 channels */
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dw_write(dma, DW_MASK_TFR, INT_MASK_ALL);
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dw_write(dma, DW_MASK_BLOCK, INT_MASK_ALL);
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dw_write(dma, DW_MASK_SRC_TRAN, INT_MASK_ALL);
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dw_write(dma, DW_MASK_DST_TRAN, INT_MASK_ALL);
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dw_write(dma, DW_MASK_ERR, INT_MASK_ALL);
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#ifdef DW_FIFO_PARTITION
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/* TODO: we cannot config DMA FIFOs if DMAC has been already */
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/* allocate FIFO partitions, 128 bytes for each ch */
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dw_write(dma, DW_FIFO_PART1_LO, 0x100080);
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dw_write(dma, DW_FIFO_PART1_HI, 0x100080);
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dw_write(dma, DW_FIFO_PART0_HI, 0x100080);
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dw_write(dma, DW_FIFO_PART0_LO, 0x100080 | (1 << 26));
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dw_write(dma, DW_FIFO_PART0_LO, 0x100080);
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#endif
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/* set channel priorities */
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for (i = 0; i < DW_MAX_CHAN; i++) {
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#if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \
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|| defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE
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dw_write(dma, DW_CTRL_HIGH(i), DW_CTLH_CLASS(dp->chan[i].class));
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#else
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dw_write(dma, DW_CFG_LOW(i), DW_CFG_CLASS(dp->chan[i].class));
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#endif
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}
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}
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static int dw_dma_probe(struct dma *dma)
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{
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struct dma_pdata *dw_pdata;
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@ -999,6 +1129,7 @@ static int dw_dma_probe(struct dma *dma)
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return 0;
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}
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#endif
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const struct dma_ops dw_dma_ops = {
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.channel_get = dw_dma_channel_get,
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@ -128,6 +128,12 @@ struct dma {
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void *private;
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};
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struct dma_int {
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struct dma *dma;
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uint32_t channel;
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uint32_t irq;
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};
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struct dma *dma_get(int dmac_id);
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#define dma_set_drvdata(dma, data) \
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