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platform: cavs: remove hw clk setting in platform_init 

These hw clk settings are done in zephyr layer in power_init(),
so remove them in sof side.

The CONFIG_CAVS_LPRO_ONLY is for CoffeeLake only and doesn't affect
TigerLake, so the hw clk settings are the same for platform_init
and power_init(), then we can remove them.

Signed-off-by: Rander Wang <rander.wang@intel.com>
This commit is contained in:
Rander Wang 2023-07-06 15:57:20 +08:00 committed by Liam Girdwood
parent 1032fa30ed
commit ed6f48b94d
1 changed files with 0 additions and 20 deletions
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20
src/platform/intel/cavs/platform.c
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@ -389,26 +389,6 @@ int platform_init(struct sof *sof)
trace_point(TRACE_BOOT_PLATFORM_CPU_FREQ);
#if CONFIG_TIGERLAKE
/* initialize PM for boot */
/* request configured ring oscillator and wait for status ready */
shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | CAVS_DEFAULT_RO);
while (!(shim_read(SHIM_CLKSTS) & CAVS_DEFAULT_RO))
idelay(16);
shim_write(SHIM_CLKCTL,
CAVS_DEFAULT_RO | /* Request configured RING Osc */
CAVS_DEFAULT_RO_FOR_MEM | /* Select configured
* RING Oscillator Clk for memory
*/
SHIM_CLKCTL_HMCS_DIV2 | /* HP mem clock div by 2 */
SHIM_CLKCTL_LMCS_DIV4 | /* LP mem clock div by 4 */
SHIM_CLKCTL_TCPLCG_DIS_ALL); /* Allow Local Clk Gating */
/* prevent LP GPDMA 0&1 clock gating */
shim_write(SHIM_GPDMA_CLKCTL(0), SHIM_CLKCTL_LPGPDMAFDCGB);
shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
/* prevent DSP Common power gating */
pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);