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mailbox: unify sram fw regs 

This patch will move all sram fw regs offsets (only offsets) to a commpon
mailbox.h

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
This commit is contained in:
Adrian Bonislawski 2020-06-22 10:24:11 +02:00 committed by Liam Girdwood
parent b49080c784
commit eaf49e26b4
6 changed files with 40 additions and 40 deletions
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39
src/include/kernel/mailbox.h Normal file
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@ -0,0 +1,39 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2020 Intel Corporation. All rights reserved.
*
* Author: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
*/
/**
* \file include/kernel/mailbox.h
* \brief FW Regs API definition
* \author Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
*/
#ifndef __KERNEL_MAILBOX_H__
#define __KERNEL_MAILBOX_H__
/** \addtogroup fw_regs_api FW Regs API
* This is a common SRAM window 0 FW "registers" layout
* used in the platfrom-defined SRAM window 0 region
* @{
*/
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_1 SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_2 0x18
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_3 0x1C
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_4 0x20
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_5 0x24
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_6 0x28
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_7 0x2C
#define SRAM_REG_FW_END (SRAM_REG_FW_TRACEP_SLAVE_CORE_7 + 0x4)
/** @}*/
#endif /* __KERNEL_MAILBOX_H__ */

1
src/include/sof/lib/mailbox.h
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@ -9,6 +9,7 @@
#ifndef __SOF_LIB_MAILBOX_H__
#define __SOF_LIB_MAILBOX_H__
#include <kernel/mailbox.h>
#include <platform/lib/mailbox.h>
#include <sof/debug/panic.h>
#include <sof/lib/cache.h>

10
src/platform/apollolake/include/platform/lib/memory.h
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@ -198,16 +198,6 @@
#define SRAM_SW_REG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
#define SRAM_SW_REG_SIZE 0x1000
/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000

10
src/platform/cannonlake/include/platform/lib/memory.h
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@ -182,16 +182,6 @@
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000
/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000

10
src/platform/icelake/include/platform/lib/memory.h
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@ -180,16 +180,6 @@
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000
/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000

10
src/platform/tigerlake/include/platform/lib/memory.h
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@ -182,16 +182,6 @@
#define SRAM_SW_REG_BASE (HP_SRAM_BASE + 0x4000)
#define SRAM_SW_REG_SIZE 0x1000
/* SRAM window 0 FW "registers" */
#define SRAM_REG_ROM_STATUS 0x0
#define SRAM_REG_FW_STATUS 0x4
#define SRAM_REG_FW_TRACEP 0x8
#define SRAM_REG_FW_IPC_RECEIVED_COUNT 0xc
#define SRAM_REG_FW_IPC_PROCESSED_COUNT 0x10
#define SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE 0x14
#define SRAM_REG_FW_END \
(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE)
#define SRAM_OUTBOX_SIZE 0x1000