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mailbox: deduplication of mailbox headers for cavs 

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
This commit is contained in:
Bartosz Kokoszko 2019-02-27 11:51:27 +01:00 committed by Marcin Maka
parent 53a63eac14
commit eae1d3a31c
8 changed files with 98 additions and 177 deletions
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47
src/platform/apollolake/include/platform/mailbox.h
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@ -32,51 +32,6 @@
#ifndef __INCLUDE_PLATFORM_MAILBOX__
#define __INCLUDE_PLATFORM_MAILBOX__
#include <platform/memory.h>
/*
* The Window Region on Broxton HPSRAM is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
* +---------------------+----------------+-----------------------------------+
*/
/* window 3 - trace */
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
/* window 2 debug, exception and stream */
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
/* window 1 inbox/downlink and FW registers */
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
/* window 0 */
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
#include <cavs/mailbox.h>
#endif

47
src/platform/cannonlake/include/platform/mailbox.h
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@ -33,51 +33,6 @@
#ifndef __INCLUDE_PLATFORM_MAILBOX__
#define __INCLUDE_PLATFORM_MAILBOX__
#include <platform/memory.h>
/*
* The Window Region on Broxton HPSRAM is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
* +---------------------+----------------+-----------------------------------+
*/
/* window 3 - trace */
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
/* window 2 debug, exception and stream */
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
/* window 1 inbox/downlink and FW registers */
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
/* window 0 */
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
#include <cavs/mailbox.h>
#endif

47
src/platform/icelake/include/platform/mailbox.h
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@ -33,51 +33,6 @@
#ifndef __INCLUDE_PLATFORM_MAILBOX__
#define __INCLUDE_PLATFORM_MAILBOX__
#include <platform/memory.h>
/*
* The Window Region on Broxton HPSRAM is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
* +---------------------+----------------+-----------------------------------+
*/
/* window 3 - trace */
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
/* window 2 debug, exception and stream */
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
/* window 1 inbox/downlink and FW registers */
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
/* window 0 */
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
#include <cavs/mailbox.h>
#endif

2
src/platform/intel/cavs/CMakeLists.txt
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@ -5,3 +5,5 @@ add_local_sources(sof
memory.c
pm_runtime.c
)
target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include)

84
src/platform/intel/cavs/include/cavs/mailbox.h Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (c) 2019, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Intel Corporation nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
*/
#ifndef __INCLUDE_CAVS_MAILBOX__
#define __INCLUDE_CAVS_MAILBOX__
#include <platform/memory.h>
/*
* The Window Region on HPSRAM for cAVS platforms is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
* +---------------------+----------------+-----------------------------------+
*
* Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE
* and MAILBOX_SW_REG_BASE are equal to 0
*/
/* window 3 - trace */
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
/* window 2 debug, exception and stream */
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
/* window 1 inbox/downlink and FW registers */
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
/* window 0 */
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
#endif

40
src/platform/suecreek/include/platform/mailbox.h
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@ -33,44 +33,6 @@
#ifndef __INCLUDE_PLATFORM_MAILBOX__
#define __INCLUDE_PLATFORM_MAILBOX__
#include <platform/memory.h>
/*
* The Window Region on Suecreek HPSRAM is organised like this :-
* +--------------------------------------------------------------------------+
* | Offset | Region | Size |
* +---------------------+----------------+-----------------------------------+
* | SRAM_TRACE_BASE | Trace Buffer | SRAM_TRACE_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_DEBUG_BASE | Debug data | SRAM_DEBUG_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_INBOX_BASE | Inbox | SRAM_INBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
* | SRAM_OUTBOX_BASE | Outbox | SRAM_MAILBOX_SIZE |
* +---------------------+----------------+-----------------------------------+
*/
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
#define MAILBOX_SW_REG_SIZE 0
#define MAILBOX_SW_REG_BASE 0
#include <cavs/mailbox.h>
#endif

4
src/platform/suecreek/include/platform/memory.h
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@ -250,6 +250,10 @@
#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
#define SRAM_TRACE_SIZE 0x1000
/* Suecreek HPSRAM does not have SW_REG window*/
#define SRAM_SW_REG_BASE 0
#define SRAM_SW_REG_SIZE 0
#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)

4
test/cmocka/CMakeLists.txt
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@ -33,6 +33,10 @@ else()
set(CMOCKA_INCLUDE_DIR ${source_dir}/include)
endif()
if(CONFIG_CAVS)
target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include)
endif()
# linker script, just for log entries
set(memory_mock_lds_in ${PROJECT_SOURCE_DIR}/test/cmocka/memory_mock.x.in)
set(memory_mock_lds_out ${PROJECT_BINARY_DIR}/test/cmocka/memory_mock.x)